SOC Engineering, Principal Engineer (STA)
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is seeking a Principal Engineer specializing in Static Timing Analysis (STA) for their SOC Engineering team in Bengaluru, India. This role involves leading timing closure for advanced process nodes, utilizing industry-leading EDA tools, and requires over 12 years of relevant experience. The position emphasizes technical leadership, collaboration, and driving innovation in semiconductor design.
Responsibilities
- Independently own and drive signoff static timing analysis and timing closure for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.
- Execute static timing analysis (STA), power analysis, synthesis and timing/power closure to meet stringent performance and power targets.
- Develop and validate timing constraints at block-level or Full SoC level.
- Utilize and optimize Synopsys EDA tools, including PrimePower, PT-PX, PrimeClosure, and Tweaker to deliver state-of-the-art silicon solutions.
- Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.
- Contribute to the continuous improvement of static timing analysis flows and methodologies and best practices, sharing insights and mentoring junior engineers as needed.
Requirements
- Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.
- 12+ years of relevant experience in static timing analysis, particularly in advanced technology nodes (7nm/5nm/3nm).
- Comprehensive hands-on experience of constraints development, validation, static timing analysis (STA), power analysis, Timing and power ECO generation.
- Proficiency with Synopsys EDA tools such as PrimeTime, PT-PX, PrimeClosure, Tweaker.
- Working experience with Synopsys tools like Fusion Compiler, Design Compiler, Formality, and StarRC.
- Strong scripting and automation skills using Python, PERL, TCL, or similar languages.
- Solid understanding of timing constraints development, validation, static timing analysis and closure, for both block-level and full-chip designs.
- Exposure to high-frequency design and low-power design methodologies.
- Proactive, self-motivated, and driven to achieve technical excellence.
- Exceptional problem-solving and analytical skills with a keen attention to detail.
- Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.
- Collaborative team player who values knowledge sharing and mentoring others.
- Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.
Desired Qualifications
- Knowledge of synthesis, clock tree structures, implementation and STA tool correlation, impact of constraints on physical implementation, parasitic extraction, and formal verification will be preferred.
Benefits
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.
#SOC#Engineering#Principal Engineer#STA#Static Timing Analysis#semiconductor#chip design#circuit design#verification#tapeout#EDA tools
Company
Synopsys Inc
Job Posted
4 days ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bengaluru, India
Qualification
Bachelor, Master
Applicants
Be an early applicant