SOC Engineering, Principal Engineer (DFT)
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Synopsys is seeking a Principal Engineer (DFT) in Noida, India, to lead DFT architecture and implementation for complex SoCs. This role requires extensive experience with scan/ATPG and BIST, a strong understanding of the SoC design flow, and the ability to collaborate cross-functionally to ensure silicon success and optimize production test costs.
Responsibilities
- Own DFT architecture, implementation, integration, and verification for complex SoCs/subsystems.
- Define and execute test strategies across scan insertion and ATPG, memory BIST, logic BIST, and analog/PHY test considerations.
- Drive DFT signoff readiness by identifying testability risks early and proposing design changes.
- Develop and institutionalize reusable DFT methodologies, checklists, and guidelines.
- Partner with silicon validation and test engineering teams on post-silicon debug and failure analysis.
- Collaborate with RTL design, functional verification, physical design, timing, and power teams.
- Provide technical guidance to peers through design reviews and best-practice sharing.
Requirements
- Bachelor’s or Master’s degree in Electronics Engineering, Electrical Engineering, or related field.
- Typically 10+ years of hands-on SoC DFT experience.
- Proven depth in scan/ATPG, memory BIST, logic BIST, and analog test considerations.
- Strong understanding of the end-to-end SoC design flow.
- Demonstrated experience owning DFT implementation for complex SoCs that have taped out and gone to production.
- Proven ability to work cross-functionally to resolve testability issues and drive closure under schedule constraints.
- Ability to quickly identify untestable logic or weak test hooks and propose practical fixes.
- Comfortable leading technical discussions with architects and pushing back when decisions introduce coverage gaps or yield risk.
- High ownership and ambiguity tolerance—able to define a path forward with incomplete information.
- Clear communication, translating DFT tradeoffs into schedule/cost/yield impact for stakeholders.
Desired Qualifications
- Strong working knowledge of Synopsys DFT tools such as TetraMAX, DFT Compiler, and/or BIST Architect (plus).
- Post-silicon debug experience and collaboration with test engineering teams to refine production test programs (plus).
- Operate with high ownership and ambiguity tolerance—able to define a path forward with incomplete information.
- Share expertise through hands-on collaboration, reviews, and problem-solving.
- Stay current with evolving DFT techniques.
Benefits
- Comprehensive medical and healthcare plans.
- ETO and FTO Programs (Time Away).
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- ESPP (Purchase Synopsys common stock at a 15% discount).
- Retirement Plans.
- Competitive salaries.
#DFT#SOC#Engineering#ATPG#BIST#Hardware Engineering#Semiconductor
Company
Synopsys Inc
Job Posted
1 day ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
Noida, India
Qualification
Bachelor, Master
Applicants
Be an early applicant