SOC Engineering, Principal Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is looking for a Principal Engineer for their SOC Engineering team in Austin, Texas. This role involves leading complex ASIC/SoC design verification from planning through sign-off, requiring deep expertise in SystemVerilog/UVM and processor-based SoC architectures. The ideal candidate will have 15+ years of experience and a proven track record of leading verification teams through multiple tape-outs.
Responsibilities
- Lead subsystem and SoC verification from requirements review and planning through environment development, regression execution, coverage closure, and sign-off.
- Translate specifications into verification plans, test scenarios, coverage models, checkers, and traceable acceptance criteria.
- Architect reusable SystemVerilog/UVM environments integrating commercial VIP, processor models, register models, assertions, reference models, and scoreboards.
- Verify processor and system integration, including boot flows, address mapping, memory access, coherency, interrupts, timers, debug, and configuration interfaces.
- Drive verification of clock switching and gating, reset sequencing, power-state transitions, isolation, retention, and cross-domain dependencies.
- Verify fault-management and recovery behavior, including error capture, masking, aggregation, ECC/parity, watchdogs, monitors, and error injection.
- Develop directed, constrained-random, and embedded C tests covering concurrent traffic, corner cases, initialization, and failure/recovery sequences.
- Lead root-cause debug across RTL, verification environments, firmware, and third-party IP; coordinate fixes and verify resolution.
- Own regression health, defect tracking, requirements traceability, functional/code coverage, milestone readiness, and sign-off evidence.
- Mentor engineers and coordinate technical execution with architecture, design, firmware, formal verification, and other engineering teams.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
- 15+ years of ASIC/SoC design verification experience, including hands-on subsystem or full-chip ownership through multiple tape-outs.
- Proven experience leading verification teams and driving technical execution through major milestones and sign-off.
- Strong SystemVerilog/UVM expertise, including constrained-random stimulus, assertions, functional coverage, scoreboards, and register models.
- Deep understanding of processor-based SoC architectures, including multicore integration, memory hierarchy, coherent interconnects, interrupts, boot, and debug.
- Hands-on experience verifying clock, reset, and power-control logic, including sequencing, state transitions, dependencies, and recovery behavior.
- Experience verifying hardware fault-management mechanisms, including error reporting, masking, ECC/parity, error injection, and fault recovery.
- Working knowledge of AMBA interfaces and coherent interconnect protocols, with practical system-level transaction-debug experience.
- Embedded C/C++ experience for initialization, processor-driven tests, interrupt handling, and hardware/software debug.
- Strong capability in regression management, coverage analysis, requirements traceability, and verification closure.
- Experience with simulation, waveform-debug, and verification-management tools, plus scripting in Python, Tcl, or shell.
- Strong communication skills and experience working with customers and geographically distributed teams.
Desired Qualifications
- Low-power verification using UPF and power-aware simulation.
- Lockstep verification and requirements-based verification for safety-critical designs.
- Formal verification and assertion-based verification experience.
- Emulation experience, including platform bring-up, software-driven testing, or simulation-to-emulation test reuse, is a plus.
- Experience with Synopsys VCS, Verdi, VC Formal, and verification-management tools.
Benefits
- Comprehensive medical and healthcare plans that work for you and your family.
- ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.
- Annual bonus, equity, and other discretionary bonuses.
- Comprehensive health, wellness, and financial benefits as part of a competitive total rewards package.
Skills
SystemVerilogUVMAMBAEmbedded CPythonTcl
#SOC Engineering#Principal Engineer#ASIC/SoC design verification#SystemVerilog#UVM#multicore integration#memory hierarchy#coherent interconnects#interrupts#boot#debug#clock#reset#power-control logic#fault-management#AMBA#Embedded C/C++#regression management#coverage analysis#requirements traceability#verification closure#simulation#waveform-debug#verification-management tools#Python#Tcl#shell scripting#customer communication#distributed teams
About Synopsys Inc
Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…
Company
Synopsys IncJob Posted
2 days ago
Employment Type
Full Time
Work mode
On Site
Salary
US$171,200–256,800 / year
Experience Level
Executive
Locations
Austin, United States
Qualification
Bachelor, Master
Applicants
Be an early applicant
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