Soc Engineer (synthesis/timing) -18607
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Synopsys is hiring a SOC Engineer in Ho Chi Minh City, Vietnam, focusing on synthesis and timing for ASIC/SOC projects. Responsibilities include synthesis, LEC, STA, and LDRC, using Synopsys EDA tools and IP to solve customer problems and contribute to design projects.
Responsibilities
- Synthesis
- LEC
- LDRC
- GCA
- STA
- PTPX
- Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team.
- Contributes to both turnkey projects and as a trusted advisor to customer design.
- Develop innovative solutions to problems with little guidance and implement them independently.
- Set task-level goals and consistently meet schedules.
- Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.
Requirements
- 2 - 4 years of related experience.
- Good of ASIC/SOC design, synthesis, timing closure.
- Familiar with Synthesis, LEC, STA flow.
- Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous.
- Familiar with scripting languages, such as TCL, Perl, Python.
- Good English/communication skills and willingness to work with customer.
- BS or MS with an EE or related major
Desired Qualifications
- It’s a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm.
Benefits
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.
#SOC#ASIC#Synthesis#Timing Closure