SerDes Analog & DSP System, Architect - 18616
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Responsibilities
- Own the architecture of SerDes IP for PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+), from system definition through analog macro implementation.
- Interpret SerDes standards and develop system models and link budgets that translate into detailed analog and DSP specifications.
- Lead the design of analog macro-level circuits across the TX, RX, and clock paths, optimizing for power, area, and performance targets.
- Run comprehensive system and circuit simulations to verify and sign off design performance across multiple protocols and channels.
- Design and propose calibration, adaptation, and control algorithms, collaborating closely with digital RTL engineers on their implementation.
- Oversee physical layout to minimize parasitics, device stress, and process variation impacts.
- Correlate simulated performance with silicon measurements and contribute to lab testing and electrical characterization.
- Track and review the technical progress of sub-block owners and junior engineers.
- Present technical insights for peer and customer reviews, and support customers on system-level issues.
- Document design features, methodologies, and test plans for internal and customer use.
Requirements
- PhD with 10+ years, or MSc with 12+ years of SerDes/high-speed analog and mixed-signal design experience.
- Silicon-proven, transistor-level design experience in TX, RX, and clock paths within SerDes architectures.
- In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers/deserializers, VCOs, phase interpolators, PLLs, ADCs, and DACs.
- Solid understanding of DSP and communications theory, including equalization, encoding, and noise/crosstalk filtering.
- Strong experience modeling systems in MATLAB/Simulink and analyzing link budgets for PAM4 serial links.
- Experience with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
- Proficiency with EDA tools and SPICE simulators, plus hands-on lab testing of high-speed serial links.
- Programming experience in Verilog-A, SystemVerilog, C, TCL, and Python.
Desired Qualifications
- Innovative, analytical thinker with exceptional problem-solving skills.
- Collaborative leader who thrives in a multidisciplinary environment.
- Effective communicator, able to translate complex concepts for diverse audiences.
- Detail-oriented and methodical in approach.
- Adaptable and eager to learn, keeping pace with evolving technologies.
- Mentor and role model for junior engineers.
- Customer-focused and proactive in driving project outcomes.
Benefits
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement plans
- Competitive salaries
- Eligible for an annual bonus, equity, and other discretionary bonuses
- Comprehensive health, wellness, and financial benefits
Skills
Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…
Company
Synopsys IncJob Posted
2 days ago
Employment Type
Full Time
Work mode
On Site
Salary
US$192,000–288,000 / year
Experience Level
Senior
Locations
Boxborough, United States
Sunnyvale, United States
Mississauga, Canada
Qualification
Applicants
Be an early applicant
