Senior Technical Architect
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
As a Senior Technical Architect in Bangalore, India, you will define ASIC/SoC verification strategy, develop full chip testplans, and architect UVM-based testbenches. This role requires 8-14 years of experience with SystemVerilog, Verilog, UVM, and scripting languages, plus expertise in high-speed protocols and EDA tools.
Responsibilities
- Define ASIC/SoC verification strategy.
- Develop full chip testplans.
- Define full chip TB architecture.
- Develop UVM-based testbenches using SystemVerilog.
- Implement SV functional coverage and assertions.
- Develop TB components for SOC with C and SV.
- Code, execute, and debug test cases.
- Set up functional coverage and write system assertions.
- Analyze code coverage metrics.
- Debug simulation failures using waveform viewer tools.
- Code and debug SOC C based tests.
- Perform Gate Level Simulation and netlist debugging.
- Perform regression failure analysis.
- Achieve Functional and Code Coverage closure.
- Automate regression tests and parse log files using Perl/Shell scripting.
- Collaborate with hardware design team to resolve bug reports.
- Document test plans, micro-architecture specifications, and verification results.
- Design and architect large-scale solutions ensuring scalability, performance, and security.
- Train and develop team members.
- Continuously upskill with cutting-edge technology.
- Leverage domain/tech expertise to gather client needs, deliver solutions, and craft technology strategy.
Requirements
- 8 to 14 years of experience is mandatory.
- Good understanding of ASIC/SoC life cycle.
- Participated in multiple ASIC/SoC verification till tapeout stage.
- Experience writing ASIC/SoC testplans.
- Experience in ASIC/SoC Testbench definition.
- Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and UVM.
- Expertise & hands-on experience in OVM/UVM methodologies using SV.
- Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.
- Experience in developing TB components for SOC with C, SV.
- Experience in developing TB components, including functional coverage implementation and assertion coding.
- Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics.
- Experience in SOC C based tests coding & debugging.
- Experience in Gate level simulation & netlist debugging.
- Experience in regression failure analysis, Functional and Code Coverage closure.
- Experience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulation log files.
- Experience in Collaborating closely with the hardware design team to analyze, document, and resolve bug reports efficiently.
- Experience in Document test plans, micro-architecture specifications, and verification results for team reviews.
- Proven industry experience in ASIC/SoC design and verification with multiple successful tape-outs.
- Mastery of SystemVerilog, Verilog, and UVM.
- Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.
- Strong understanding of CPU/GPU architectures, cache coherency, and memory controllers (e.g., DDR4/DDR5, HBM) is highly desirable.
- Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms.
- Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C, PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE).
- Advanced capability in Python, Tcl, or Perl to create custom automation infrastructure for regressions and metrics tracking.
- Ability to foresee technical risks weeks or months in advance and proactively implement mitigation strategies.
- Strong leadership and communication skills to guide cross-functional teams and align stakeholders on technical directions.
Desired Qualifications
- Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field.
#ASIC#SoC#verification#technical architect#SystemVerilog#UVM#VCS#QuestaSim#Xcelium#Verd#Python#Perl#Shell Scripting#AXI#CHI#ACE#PCIe#NVMe#Ethernet#USB#SPI#I2C#DDR4#DDR5#HBM
Company
HCLTech
Job Posted
2 days ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bangalore, India
Qualification
Bachelor, Master
Applicants
Be an early applicant