Senior Silicon Design Verification Engineer, Google Cloud

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Google Cloud seeks a Senior Silicon Design Verification Engineer in Bengaluru, India, to drive progress and mentor junior team members in verification of digital logic for FPGAs or ASICs, particularly in the networking domain. The role involves planning verification, creating environments using SystemVerilog and UVM, and debugging designs to ensure functional correctness.

Responsibilities

Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology.
Verify designs with SystemVerilog Assertions and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.
Experience in verification and debug of IP/subsystem/SoCs in the networking domain such as packet processing, bandwidth management, and congestion control.
Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

Desired Qualifications

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with performance verification of ASICs and ASIC components.
Experience with ASIC standard interfaces and memory system architecture.
Experience in artificial intelligence/machine learning (AI/ML) accelerators or vector processing units.

Benefits

Equity is granted exclusively and discretionarily by Alphabet Inc.

Skills

SystemVerilogSpecmanEFPGAASICUVM

#Google Cloud#Silicon Design#Verification#ASIC#FPGA#RTL#SystemVerilog#Networking

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