Senior Lead Physical Design Engineer

Construction, Engineering & Trades · Civil & Industrial Engineering · Electrical Engineering

In short

Qualcomm is seeking a Senior Lead Physical Design Engineer in Noida, India, to own PNR implementation for their SoCs on the latest nodes. This role requires hands-on experience in floorplanning, PNR, STA, and signoff domains, along with strong scripting skills in Unix/Linux.

Responsibilities

Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes.
Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc).

Requirements

Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
5+ years Hardware Engineering experience or related work experience.
5+ years' experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm).
Good hands-on experience on Floorplanning, PNR and STA flows.
Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc.
Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc.
Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting.
Quick learner with good analytical and problem-solving skills.

Desired Qualifications

PNR implementation for Qualcomm SoC's

Benefits

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process.