Senior Emulation Performance Methodology & Debug Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems · QA & Testing
In short
Qualcomm is looking for a Senior Emulation Performance Methodology & Debug Engineer to join their Emulation Team in San Diego. The role involves working with emulation platforms and tools to support SoC pre-silicon development, requiring expertise in hardware, software, and various programming languages.
Responsibilities
- Design, development, and deployment of uniform global methodologies for emulation build generation and debug across FPGA based emulation platforms.
- Cross-site collaboration, vendor engagements, and executive communication.
- Pre-silicon prototyping for new SoC designs, including pre-silicon enablement and bring-up.
- Bring-up of new FPGA emulation/prototyping hardware and software.
- Debugging low level software and hardware issues.
- Validation and debug of digital circuits.
- Work with emulation platforms (FPGA Prototyping, Veloce, Palladium), emulation tools (Synthesis, Place and Route, Constraints, Clocking, Timing Closure), and System Debug (Waveform generation and Content Debug support).
- Support SoC Functionality (CPU/DSP Core, Multimedia, IO, Peripherals, DDR, Modem, Bus Protocols).
Requirements
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- OR PhD in Science, Engineering, or related field.
- Expertise in Verilog / SystemVerilog.
- Experience with C programming.
- Proficient in Python, TCL.
- FPGA Expertise: Xilinx/Intel FPGAs, Tools, and timing closure techniques.
Desired Qualifications
- 5+ years of experience working in emulation and silicon environments.
- Experience in CPU and SoC architectures, with solid understanding of SoC building blocks (interconnects, power management, PMIC, NoC, peripherals).
- Basic understanding of power and performance.
- Experience with debug tools including JTAG and kernel debuggers.
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package designed to support your success at work, at home, and at play.
- Reasonable accommodations to support individuals with disabilities to be able to participate in the hiring process.
- Accessible workplace for individuals with disabilities.
#ASIC Design#Verification#Validation#Integration#Emulation#Silicon Environments#FPGA Prototyping#Veloce#Palladium#SoC#CPU#DSP#Multimedia#IO#Peripherals#DDR#Modem#Bus Protocols#Debug#JTAG#Kernel Debuggers#Verilog#SystemVerilog#C programming#Python#TCL#Xilinx FPGAs#Intel FPGAs