Senior Designer - Design Validation

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

HCLTech is seeking a Senior Designer for Design Validation in Chennai, India. The role involves defining ASIC/SoC verification strategy, developing testplans, and building UVM-based testbenches using SystemVerilog. Experience with Gate Level Simulation, regressions, and coverage analysis is essential.

Responsibilities

Define ASIC/SoC verification strategy.
Develop full chip testplans.
Define full chip TB Architecture.
Develop UVM based testbenches.
Develop C based TB.
Write SV functional coverage and Assertions.
Develop, code, execute, and analyze test cases and bugs.
Perform Gate Level Simulation.
Manage regressions and coverage analysis.
Understand ASIC/SoC life cycle.
Write ASIC/SoC testplans and verification strategy documents.
Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and UVM.
Develop TB components for SOC with C and SV.
Write, execute, and debug constrained-random and directed test cases.
Implement functional coverage and write system assertions (SVA).
Analyze code coverage metrics.
Debug complex simulation failures using waveform viewer tools.
Code and debug SOC C based tests.
Perform Gate level simulation and netlist debugging.
Analyze regression failures and achieve functional and code coverage closure.

Requirements

Proficiency in Verilog, SystemVerilog, and UVM.
Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.
Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi).
Basic understanding of standard bus protocols like AMBA (AXI, AHB, APB) or peripheral protocols (SPI, I2C, PCIe).
Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation.
Experience writing ASIC/SoC testplans.
Experience writing verification strategy documents.
Experience in ASIC/SoC Testbench definition.
Expertise and hands-on experience in OVM/UVM methodologies using SV.
Experience developing TB components, including functional coverage implementation and assertion coding.
Experience in Gate level simulation & netlist debugging.
Experience in regression failure analysis.
Functional and Code Coverage closure.

Desired Qualifications

Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field.

Benefits

Supercharge your potential.
Find your career.
Find your spark.
A place that knows that helping its customers stay on top starts by putting its people first.

Skills

VerilogSystemVerilogUVMDigital LogicFinite State Machines (FSM)FIFO ArchitecturesClocking ConceptsSynopsys VCSSiemens QuestaSimCadence XceliumVerdiAMBAAXIAHBAPBSPII2CPCIeLinuxPythonTclPerlC

#ASIC#SoC#Verification#Testplan#TB Architecture#UVM#SystemVerilog#Digital Logic Design#EDA Tools#Protocols#Scripting

About HCLTech

Supercharging progress through technology and innovation

HCLTech is a global technology company, home to 219,000+ people across 54 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2022 totaled $12.1 billion. To learn how we can supercharge progress for…

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