Senior Designer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
This Senior Designer position in Bangalore, India, requires 2-4 years of experience in ASIC/SoC verification, including testplan and testbench development using UVM and SystemVerilog. Responsibilities include developing C-based test components, functional coverage, assertion coding, and gate-level simulations. Familiarity with digital logic design, EDA tools, and scripting languages is essential.
Responsibilities
- Work closely with stakeholders to understand and refine design requirements.
- Develop prototypes and proof-of-concept implementations to validate design decisions.
- Mentor junior designers, share knowledge and expertise through training sessions and documentation.
- Collaborate with cross-functional teams and other stakeholders to align software design with overall project goals.
- Work with quality assurance teams to establish and maintain high quality.
Requirements
- 2 to 4 years' experience is mandatory.
- Good understanding of ASIC/SoC life cycle.
- Experience writing ASIC/SoC testplans.
- Experience in writing verification strategy document.
- UVM based testbench development experience, including testbench definition.
- Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and UVM.
- C based TB development experience for SOC with C, SV.
- SV functional coverage, Assertions coding expertise & hands-on experience in OVM/UVM methodologies using SV.
- Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.
- Experience in developing TB components, including functional coverage implementation and assertion coding.
- Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
- Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.
- Experience in SOC C based tests coding & debugging.
- Experience in Gate level simulation & netlist debugging.
- Experience in regression failure analysis.
- Functional and Code Coverage closure.
- Proficiency in Verilog, SystemVerilog, and core concepts of UVM.
- Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.
- Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence celium/Verdi).
- Basic understanding of standard bus protocols like AMBA (AXI, AHB, APB) or peripheral protocols (SPI, I2C, PCIe).
- Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation.
#ASIC#SoC#verification#testplan#testbench#UVM#SystemVerilog#C#OVM#digital logic#FSM#FIFO#clocking#EDA tools#simulation#debugging#AMBA#AXI#AHB#APB#SPI#I2C#PCIe#Linux#Python#Tcl#Perl
Company
HCLTech
Job Posted
2 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
Bangalore, India
Applicants
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