Security Digital Design Engineer, Staff

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems · Cybersecurity

In short

Synopsys is seeking a Staff Security Digital Design Engineer in Moreira, Portugal, to design and verify secure hardware IP. This role requires expertise in RTL design (Verilog, SystemVerilog) and verification (UVM), with a focus on integrating security into IP from the start for AI, High Performance Computing, and Automotive applications.

Responsibilities

  • Design and implement RTL in Verilog and SystemVerilog for Security IP cores.
  • Build and maintain test environments for digital hardware Security IP using SystemVerilog and UVM.
  • Verify IP cores and subsystems using modern verification techniques including UVM testbenches and formal verification tools.
  • Collaborate with hardware and software security engineers to analyse functional correctness and performance of embedded IP solutions across threat models.
  • Contribute to detailed design specifications, verification plans, and documentation.
  • Work within an international team across time zones, coordinating design reviews, debugging sessions, and milestone deliveries.

Requirements

  • MSc or PhD in Electrical Engineering or Computer Science.
  • 3+ years of strong working knowledge of RTL design for hardware IP components, with hands-on experience writing synthesizable SystemVerilog.
  • Ability to create detailed specifications for test environments.
  • Proficiency in ASIC verification using System Verilog, UVM, and or Verilog.
  • Strong understanding of IC Design flows and exceptional problem-solving and debugging skills.
  • Experience with hardware security concepts or cryptographic IP is a plus.

Desired Qualifications

  • You are a passionate and skilled ASIC Digital Design Engineer with knowledge in RTL design and verification and focus on building hardware that must be both performant and secure.
  • You have a keen interest in working on cutting-edge technologies and are eager to contribute to the development of state-of-the-art IP cores and subsystems.
  • You thrive in a collaborative environment and are excited about the opportunity to work with an international team of experts.
  • You possess excellent problem-solving and debugging skills and are adept at communicating complex technical concepts effectively.
  • You are committed to continuous learning and professional growth.
  • A strong communicator with excellent written and verbal skills.
  • A team player who thrives in a collaborative international environment.
  • An innovative thinker who is passionate about technology and continuous improvement.
  • Detail-oriented and committed to delivering high-quality work.
  • Adaptable and able to manage multiple tasks effectively.

Benefits

  • Competitive salaries.
  • Comprehensive medical and healthcare plans.
  • ETO and FTO Programs for time away.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
  • ESPP to purchase Synopsys common stock at a 15% discount.
  • Retirement plans that vary by region and country.

Skills

VerilogSystemVerilogUVM
#hardware#engineering#security#rtl design#verification#asic#ip cores#semiconductor
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About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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Company

Synopsys Inc

Job Posted

6 days ago

Employment Type

Full Time

Work mode

On Site

Experience Level

Senior

Locations

Moreira, Portugal

Qualification

Master, Doctoral

Applicants

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