R&D Engineering, Director-18881
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is seeking an R&D Engineering Director with expertise in DFT and ATPG to define and drive test methodologies for next-generation ASIC and SoC designs. This role involves leading technical strategies, collaborating with R&D, and mentoring engineers to improve test quality and manufacturability in the semiconductor ecosystem.
Responsibilities
- Define and drive corporate and customer-facing DFT methodologies for next-generation ASIC and SoC designs.
- Serve as a technical leader and subject matter expert for Synopsys TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions.
- Lead deployment of advanced DFT architectures including scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrapper solutions, IJTAG infrastructures, and embedded test technologies.
- Architect scalable test access and instrumentation networks leveraging IEEE 1149.1, IEEE 1149.6, IEEE 1687 (IJTAG), and IEEE 1500 standards.
- Develop best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization.
- Drive adoption of reusable methodologies, automation frameworks, and signoff criteria across multiple programs and business units.
- Collaborate with R&D organizations to influence future product capabilities and roadmap priorities.
- Provide technical leadership for strategic customer engagements, methodology reviews, and complex technical escalations.
- Mentor engineers across multiple teams and contribute to the development of the organization's DFT expertise.
Requirements
- BS/MS in Electrical Engineering, Computer Engineering, or related field.
- 15+ years of experience in Semiconductor or EDA industry with a focus on DFT, ATPG, and manufacturing test methodologies.
- Demonstrated expertise in architecting and implementing DFT solutions for large-scale ASIC and SoC designs.
- Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions.
- Strong understanding of Scan insertion and scan compression.
- Strong understanding of Hierarchical DFT methodologies.
- Strong understanding of ATPG and diagnosis.
- Strong understanding of Stuck-at, transition, path-delay, bridge, and cell-aware fault models.
- Strong understanding of Coverage analysis and optimization.
- Strong understanding of Test cost and pattern count reduction techniques.
- Expertise with standards including IEEE 1149.1 (JTAG), IEEE 1149.6 (AC JTAG), IEEE 1687 (IJTAG), and IEEE 1500.
- Experience developing and deploying JTAG / TAP Architectures.
- Experience developing and deploying Boundary Scan Networks.
- Experience developing and deploying IJTAG Instrumentation Networks.
- Experience developing and deploying Embedded Instrument Access Solutions.
- Expertise in deploying and integrating DFT IP including Codec / Embedded Compression, OCC (On-Chip Clock Controller), LBIST, TAP Controllers, JTAG and IJTAG Infrastructure, TDR Networks, IEEE 1500 Wrappers.
- Strong understanding of RTL-to-GDSII implementation flows and interactions between DFT, synthesis, physical design, timing closure, and signoff.
- Proficiency with Tcl, Python, Perl, Shell, or similar scripting languages for methodology development and automation.
Desired Qualifications
- Recognized expert in DFT architecture and test methodology deployment.
- Experience defining enterprise-wide DFT standards and signoff methodologies.
- Strong background supporting advanced-node ASICs and multi-billion gate SoCs.
- Experience with silicon bring-up, diagnosis, yield improvement, and production ramp.
- Knowledge of functional safety standards and test requirements for automotive applications.
- Experience collaborating directly with semiconductor customers in applications engineering, consulting, or methodology leadership roles.
- Contributions to industry test standards, technical publications, patents, or conference presentations are highly valued.
Benefits
- Annual bonus, equity, and other discretionary bonuses.
- Comprehensive health, wellness, and financial benefits.
- Competitive total rewards package.
- Comprehensive medical and healthcare plans.
- ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Retirement plans that vary by region and country.
- Competitive salaries.
Skills
AIMLGenAICloudDFTATPGscan compressionhierarchical DFTboundary scanIEEE 1500IJTAGembedded testIEEE 1149.1IEEE 1149.6IEEE 1687JTAGTAP ArchitecturesEmbedded Instrument AccessCodecEmbedded CompressionOCCLBISTTAP ControllersTDR NetworksTclPythonPerlShell
#EDA#chip design#verification#manufacturing#AI#ML#GenAI#Cloud#semiconductor#ASIC#SoC#DFT#ATPG#TestMAX#IEEE 1149.1#IEEE 1149.6#IEEE 1500#IEEE 1687#IJTAG
About Synopsys Inc
Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…
Company
Synopsys IncJob Posted
4 days ago
Employment Type
Full Time
Work mode
On Site
Salary
US$230,000–344,000 / year
Experience Level
Executive
Locations
Sunnyvale, United States
Qualification
Bachelor, Master
Applicants
Be an early applicant
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