Principal Silicon Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Responsibilities
- Own and drive microarchitecture and RTL design for complex silicon blocks and subsystems, translating architecture and system requirements into clean, efficient, and high-quality hardware implementations.
- Lead the capture and validation of design intent for digital and mixed‑signal blocks, ensuring accurate constraints and seamless integration across front‑end and physical design flows.
- Provide static timing leadership for mixed‑signal interfaces, driving timing closure, exception quality, and correlation across MMMC corners.
- Partner closely with RTL, PD, mixed‑signal, DFT, and CAD teams to resolve cross‑domain issues and maintain alignment on timing, power, and functional requirements.
- Contribute to design automation including leveraging AI, constraint‑checking, and flow improvements that enhance execution efficiency and PPA.
- Operate with limited direction, demonstrating strong ownership, attention to detail, and the ability to communicate clear, data‑driven status, risks, and mitigation plans to program leadership.
Requirements
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
- Ability to meet Microsoft, customer and/or government security screening requirements.
- Pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- Provide either proof of their country of citizenship or proof of their US. residency or other protected status for assessment of eligibility to access export-controlled information.
- Verification of citizenship with a valid passport.
- 8+ years of experience in RTL design and design checks (CDC/RDC/VCLP/LINT).
- 8+ years of experience in Synthesis, Timing constraints and Power Performance Area (PPA) trade-offs.
- Proficiency in RTL to Physical Design collateral development including timing and synthesis constraints.
- Hands‑on experience with industry tools for synthesis, STA, and PD flows (e.g., PrimeTime, Genus/DC, Innovus/ICC2).
- Proficiency in recent synthesis tool capabilities and methods for QoR improvement.
- Proficiency in static timing analysis.
- Proficiency in translating physical design results into feedback for flow or RTL improvement.
- Proficiency in Tcl, Python.
Desired Qualifications
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience.
- 1+ year(s) experience working on or leading projects from beginning-to-end.
- Knowledge of full RTL2GDS flow.
- Familiarity with RTL and gate-level power analysis/optimization, UPF, and power-intent verification.
Benefits
- The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year.
- In the San Francisco Bay area and New York City metropolitan area, the base pay range is USD $188,000 - $304,200 per year.
- Certain roles may be eligible for benefits and other compensation.
Skills
Every company has a mission. What's ours? To empower every person and every organization to achieve more. We believe technology can and should be a force for good and that meaningful innovation contributes to a brighter world in the future and today. Our culture doesn’t just encourage curiosity; it embraces it. Each day we make progress together by showing up as our authentic selves. We show up with a learn-it-all mentality. We show up cheering on others, knowing their success doesn't diminish our own. We show up every day open to learning our own biases, changing our behavior, and inviting…
Company
MicrosoftJob Posted
1 day ago
Employment Type
Full Time
Work mode
Hybrid
Salary
US$142,800–274,800 / year
Experience Level
Senior
Locations
United States
Qualification
Applicants
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