Principal Digital Methodology Engineer - Design for Testability (DFT)

Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing

In short

Synopsys is looking for a Principal Digital Methodology Engineer with over a decade of experience in architecting test solutions for chips. This role involves defining and driving DFT methodologies, leading the deployment of advanced test solutions, and architecting scalable test access infrastructures for complex designs. The ideal candidate will have deep technical knowledge and hands-on experience with Synopsys TestMAX DFT and ATPG solutions.

Responsibilities

Define and drive DFT methodologies for next-generation ASIC and SoC designs across strategic customer programs, translating architecture decisions into deployable best practices.
Lead deployment of advanced test solutions including scan compression, hierarchical DFT, IEEE 1500 wrappers, IJTAG instrumentation networks, and embedded test IP across multi-billion-gate designs.
Architect scalable test access infrastructures using IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500 standards for complex multi-die and chiplet-based systems.
Develop automation frameworks, signoff criteria, and reusable methodology packages using Tcl, Python, and Perl that accelerate adoption across business units.
Serve as technical leader and subject matter expert for Synopsys TestMAX DFT, TestMAX ATPG, diagnosis, and silicon lifecycle solutions in customer engagements and internal escalations.
Collaborate directly with R&D teams to influence TestMAX product roadmap based on real deployment challenges and customer requirements.
Provide technical leadership for strategic customer engagements, methodology reviews, and complex DFT architecture decisions that impact tapeout schedules and silicon success.

Requirements

Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field.
15+ years in semiconductor or EDA industry with at least 5 years focused on DFT architecture, ATPG, and manufacturing test methodologies.
Demonstrated expertise architecting and implementing DFT solutions for large-scale ASIC and SoC designs, including successful tapeouts.
Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions in production design environments.
Deep technical knowledge of scan insertion, scan compression, hierarchical DFT, ATPG and diagnosis, stuck-at/transition/path-delay/bridge/cell-aware fault models, and coverage optimization techniques.
Expertise deploying IEEE 1149.1 (JTAG), IEEE 1149.6 (AC JTAG), IEEE 1687 (IJTAG), and IEEE 1500 standards in complex test access architectures.
Experience integrating DFT IP including Codec/embedded compression, OCC, LBIST, TAP controllers, JTAG and IJTAG infrastructure, TDR networks, and IEEE 1500 wrappers.
Strong understanding of RTL-to-GDSII flows and how DFT interacts with synthesis, physical design, timing closure, and signoff.
Proficiency with Tcl, Python, Perl, or Shell scripting for methodology automation and deployment.

Desired Qualifications

Experience defining enterprise-wide DFT standards and signoff methodologies is a strong plus.
Background supporting advanced-node ASICs, multi-billion-gate SoCs, silicon bring-up, diagnosis, or yield improvement is highly valued.
Knowledge of functional safety standards and automotive test requirements is a plus.
Contributions to industry test standards, technical publications, patents, or conference presentations strengthen your candidacy.

Benefits

Comprehensive medical and healthcare plans.
ETO and FTO Programs.
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
Retirement plans.
Competitive salaries.

Skills

AIMLGenAICloudTclPythonPerlShell scripting

#Digital Methodology Engineer#Design for Testability#DFT#ASIC#SoC#EDA#semiconductor

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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