The Job

Physical Design Engineer

Construction, Engineering & Trades · Civil & Industrial Engineering · Electrical Engineering

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In short

Qualcomm is seeking a Physical Design Engineer in Bangalore, India, to plan, design, and optimize electronic systems for next-generation products. This role requires expertise in Netlist2GDS, including floorplan, place and route, STA, and low power design implementation with UPF. A Bachelor's degree and 3+ years of physical design experience are necessary.

Responsibilities

  • Plan, design, optimize, verify, and test electronic systems, circuits, and equipment.
  • Execute complete Netlist2GDS flow: Floorplan, place and route (PnR), and sign-off convergence.
  • Perform Static Timing Analysis (STA) and sign-off optimizations.
  • Meet demanding Power, Performance, and Area (PPA) requirements for complex subsystems/SoCs.
  • Implement low power design features, including Unified Power Format (UPF), multi-voltage domains, and power gating.
  • Work on multiple technology nodes in advanced processes.
  • Drive automation to improve PPA.
  • Manage and drive a small team for project execution and PPA targets.

Requirements

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field and 6+ years of Hardware Engineering experience.
  • Master's degree in Computer Science, Electrical/Electronics Engineering, or related field and 5+ years of Hardware Engineering experience.
  • PhD in Computer Science, Electrical/Electronics Engineering, or related field and 4+ years of Hardware Engineering experience.
  • Bachelor’s or Master’s degree from a top-tier institute.
  • 3 years of experience in physical design from product-based companies.
  • Proven experience in managing complex subsystems and small teams.
  • Proficiency in complete Netlist2GDS: Floorplan, place and route (PnR), and sign-off convergence.
  • Proficiency in Static Timing Analysis (STA) and sign-off optimizations.
  • Hand-on experience in lower technology nodes.
  • Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration.
  • Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating.
  • Familiarity with ASIC design flows and physical design methodologies.
  • Strong understanding of circuit design, device physics, and deep sub-micron technology.
  • Experience working on multiple technology nodes in advanced processes.
  • Proficiency in automation to drive improvements in PPA.
  • Managing and driving a small team for project execution and PPA targets.

Desired Qualifications

  • Familiarity with ASIC design flows and physical design methodologies.
  • Strong understanding of circuit design, device physics, and deep sub-micron technology.
#Physical Design#Hardware Engineering#SoCs#ASIC#Netlist2GDS#Floorplan#Place and Route#STA#Low Power Design#UPF
Qualcomm Logo

Company

Qualcomm

Job Posted

1 month ago

Employment Type

Full Time

WorkMode

On Site

Experience Level

Senior

Locations

Bangalore, India

Qualification

Bachelor, Master, Doctoral

Applicants

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