Physical Design Engineer, Staff
Construction, Engineering & Trades · Civil & Industrial Engineering · Electrical Engineering
In short
As a Staff Physical Design Engineer at Qualcomm in Hod Hasharon, you will lead physical implementation, timing closure, and sign-off on advanced process nodes like TSMC N5/N4P/N3. You will drive automation using Python and TCL, integrate Agentic AI methodologies, and collaborate with cross-functional teams to deliver high-performance, low-power products.
Responsibilities
- Lead floorplanning, placement, CTS, routing, and optimization for high-speed digital blocks and subsystems.
- Drive timing closure including clock skew balancing, OCV handling, MCMM analysis, and ECO implementation.
- Conduct and own signal integrity, power integrity, IR drop, and electromigration analysis (RedHawk / Voltus).
- Run full signoff verification flows (DRC, LVS, DFM, EM/IR).
- Develop and maintain backend PD flows using Python and TCL-based automation for PnR, STA, and physical verification.
- Drive Agentic AI integration — leverage AI-assisted tools for automated constraint optimization, timing ECO suggestions, and intelligent violation triage.
- Optimize power and area via Multi-Vt optimization, clock gating, and power-aware synthesis.
- Collaborate cross-functionally with front-end, DFT, verification, and process teams to resolve design and manufacturing issues.
Requirements
- 3–8 years of experience in digital Physical Design (Backend) methodologies.
- Experience with advanced process nodes (TSMC N5, N4P, N3, or equivalent FinFET).
- Proficiency in EDA tools: Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime, RedHawk / Voltus.
- Strong understanding of floorplanning, CTS, PnR, STA, IR drop/EM analysis, and power optimization.
- Solid scripting skills in Python and TCL — ability to build and maintain design automation flows.
- Hands-on flow development experience: building reusable scripts, run environments, and regression frameworks.
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Desired Qualifications
- Exposure to or curiosity about Agentic AI-driven EDA methodologies.
- Familiarity with DFT concepts (scan insertion, ATPG, BIST) is a plus.
Benefits
- Qualcomm is committed to providing an accessible process for individuals with disabilities.
- Qualcomm is committed to making our workplace accessible for individuals with disabilities.
Skills
PythonTCLAgentic AISynopsys ICC2Cadence InnovusCalibrePrimeTimeRedHawkVoltus
#ASIC#Physical Design#EDA#Python#TCL#AI
About Qualcomm
Enabling a world where everyone and everything can be intelligently connected.
Enabling a world where everyone and everything can be intelligently connected.\n\n
Company
QualcommJob Posted
4 days ago
Employment Type
Full Time
Work mode
On Site
Experience Level
Senior
Locations
Hod Hasharon, Israel
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant
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