Physical Design Engineer, Senior Lead

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is looking for a Senior Lead Physical Design Engineer in Hyderabad, India, to take ownership of the ASIC Place and Route flow from netlist to GDS2. The role involves executing thorough design checks, implementing low-power methodologies, and debugging complex issues using PnR tools and scripting languages.

Responsibilities

  • Plan, design, optimize, verify, and test electronic systems, circuits, and packaging.
  • Execute complete PD ownership from netlist to GDS2 including HM level PV, LEC, low-power checks and PDN, STA closure.
  • Implement improving existing methodologies and flows.
  • Effectively communicate the status and issues of respective owned Tasks.
  • Work in a global team environment.

Requirements

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  • PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
  • Thorough knowledge of the ASIC designs Place and Route flow and methodology.
  • Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level PV, LEC, low-power checks and PDN, STA closure.
  • Hands-on experience in Voltage Islands and low power methodologies, flows and implementation.
  • Strong background in debugging Congestion and CTS issues.
  • Expertise in PnR tools (Innovus/Fusion compiler) and flow.
  • Familiarity with Sign-off(PV/PDN/STA/FV/CLP/Scan-DRC(tk)) methodology and tools.
  • Understand and implement improving existing methodologies and flows.
  • Proficient in scripting languages (TCL,PERL,PYTHON).
  • 4-10 yrs of experience in physical design including floorplanning, PNR, CTS and signoff checks.

Desired Qualifications

  • Self-starter and highly motivated.
  • To have working experience in global team environment.
  • To be effectively communicate the status and issues of respective owned Tasks.

Benefits

  • Qualcomm is an equal opportunity employer.
  • Qualcomm is committed to providing an accessible process for individuals with disabilities.
  • Qualcomm is committed to making our workplace accessible for individuals with disabilities.
  • Qualcomm expects its employees to abide by all applicable policies and procedures.

Skills

ASIC DesignPlace and RouteGDS2PVLEClow-powerPDNSTAVoltage IslandsCongestionCTSInnovusFusion CompilerFVCLPScan-DRCTCLPERLPYTHON
#ASIC Design#Hardware Engineering#Physical Design#Place and Route#GDS2#PV#LEC#low-power#PDN#STA#Voltage Islands#Congestion#CTS#Innovus#Fusion Compiler#FV#CLP#Scan-DRC#TCL#PERL#PYTHON
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About Qualcomm

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Enabling a world where everyone and everything can be intelligently connected.\n\n

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Company

Qualcomm

Job Posted

4 days ago

Employment Type

Full Time

Work mode

On Site

Experience Level

Senior

Locations

Hyderabad, India

Qualification

Bachelor, Master, Doctoral

Applicants

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