The Job

Physical Design Engineer, Senior

Construction, Engineering & Trades · Civil & Industrial Engineering · Electrical Engineering

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In short

As a Senior Physical Design Engineer, you will lead block-level and subsystem-level physical implementation, driving timing closure and sign-off on advanced process nodes. You will also contribute to flow development and integrate AI methodologies into design automation practices.

Responsibilities

  • Lead floorplanning, placement, CTS, routing, and optimization for high-speed digital blocks and subsystems.
  • Drive timing closure including clock skew balancing, OCV handling, MCMM analysis, and ECO implementation.
  • Conduct and own signal integrity, power integrity, IR drop, and electromigration analysis (RedHawk / Voltus).
  • Run full signoff verification flows (DRC, LVS, DFM, EM/IR,).
  • Develop and maintain backend PD flows using Python and TCL-based automation for PnR, STA, and physical verification.
  • Drive Agentic AI integration — leverage AI-assisted tools for automated constraint optimization, timing ECO suggestions, and intelligent violation triage.
  • Optimize power and area via Multi-Vt optimization, clock gating, and power-aware synthesis.
  • Collaborate cross-functionally with front-end, DFT, verification, and process teams to resolve design and manufacturing issues.

Requirements

  • 3–8 years of experience in digital Physical Design (Backend) methodologies.
  • Experience with advanced process nodes (TSMC N5, N4P, N3, or equivalent FinFET).
  • Proficiency in EDA tools: Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime, RedHawk / Voltus.
  • Strong understanding of floorplanning, CTS, PnR, STA, IR drop/EM analysis, and power optimization.
  • Solid scripting skills in Python and TCL — ability to build and maintain design automation flows.
  • Hands-on flow development experience: building reusable scripts, run environments, and regression frameworks.
  • Exposure to or curiosity about Agentic AI-driven EDA methodologies.

Desired Qualifications

  • Familiarity with DFT concepts (scan insertion, ATPG, BIST) is a plus.

Benefits

  • Qualcomm is an equal opportunity employer.
  • Qualcomm is committed to providing an accessible process for individuals with disabilities.
  • Qualcomm is committed to making our workplace accessible for individuals with disabilities.
#ASIC#Physical Design#EDA#Python#TCL#AI#Process Nodes
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Company

Qualcomm

Job Posted

1 month ago

Employment Type

Full Time

WorkMode

On Site

Experience Level

Senior

Locations

Hod Hasharon, Israel

Qualification

Bachelor, Master, Doctoral

Applicants

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