PCIE SOC Application Engineer (Sr Staff)
Construction, Engineering & Trades · Civil & Industrial Engineering · Mechanical Engineering
In short
We are seeking a Sr Staff PCIE SOC Application Engineer in Dublin, Ireland to provide technical guidance and support to customers integrating Synopsys Interface IP. This role involves troubleshooting complex integration challenges and collaborating with customers throughout the SoC design flow.
Responsibilities
- Providing technical guidance and hands-on support to customers integrating Synopsys Interface IP (PCI Express and High Speed SerDes design) into their ASIC SoC/systems
- Conducting detailed integration reviews at key customer milestones and troubleshooting complex integration challenges throughout the SoC design flow.
- Collaborating with customers to resolve technical issues related to RTL simulation, synthesis, floorplanning, timing closure, and silicon/system bring-up.
- Supporting silicon bring-up and characterization in system environments, ensuring successful deployment of Synopsys IP in customer products.
- Documenting best practices, developing application notes, and delivering training to enable customer success with Synopsys solutions.
- Participating in cross-functional teams to relay customer feedback, contribute to product improvements, and stay current with the latest interface protocols and industry standards.
- Occasionally traveling to customer sites for on-site support, integration reviews, and system bring-up activities.
Requirements
- Masters with 10+yrs of Industry experience or equivalent
- At least 10 years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles (exceptional candidates with strong silicon debug and academic background considered).
- Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure.
- Hands-on expertise in integration and validation of High Speed SerDes IPs for PCIe, USB, SATA
- Proficient in RTL and gate-level simulation debugging, with familiarity in front-end tools like Design Compiler, Fusion Compiler, and PrimeTime.
- Experience with silicon bring-up and system-level characterization in lab environments.
- Domain knowledge of PCI Express and SERDES and their implementation flows.
Desired Qualifications
- Excellent communicator, able to engage effectively with customers and cross-functional teams.
- Organized and detail-oriented, with a track record of meeting tight schedules and managing multiple projects simultaneously.
- Resourceful problem-solver who adapts to new challenges and technologies with enthusiasm.
- Customer-focused, proactive, and collaborative in approach.
- Committed to continuous learning and professional growth.
Benefits
- Comprehensive range of health, wellness, and financial benefits
- Total rewards include both monetary and non-monetary offerings
- Opportunity to work with cutting-edge semiconductor technology
- Collaborative and innovative team environment
- Direct impact on industry-leading products
#Engineering#ASIC#SoC#PCI Express#SerDes