The Job

NPU STA/Timing Engineer (Senior/Lead)

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

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In short

Qualcomm is seeking a Senior/Lead NPU STA/Timing Engineer in Bangalore, India. The role involves setting up, converging, and signing off STA for complex designs, performing timing analysis and validation using tools like PT/Tempus, and optimizing STA flows. Experience with scripting and digital design flows is required.

Responsibilities

  • STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.
  • Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
  • Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
  • Evaluate multiple timing methodologies/tools on different designs and technology nodes.
  • Work on automation scripts within STA/PD tools for methodology development.
  • Good Technical writing and Communication skills, willing to work in cross-collaborative environment.
  • Experience in design automation using TCL/Perl/Python.
  • Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus.
  • Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.

Requirements

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  • PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
  • 3 - 10 years of experience in STA/Timing.
  • Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.
  • Hands-on experience with STA tools - Prime-time, Tempus.
  • Experience in driving timing convergence at Chip-level and Hard-Macro level.
  • In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling.
  • Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus).
  • Knowledge of Spice simulation Hspice/FineSim, Monte Carlo.
  • Proficient is scripting languages – TCL, Perl, Awk.
  • Basic knowledge of device physics.
  • Silicon to spice model correlation.

Desired Qualifications

  • B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.
#NPU#STA#Timing Engineer#Hardware Engineering#ASIC#VLSI
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Company

Qualcomm

Job Posted

2 weeks ago

Employment Type

Full Time

WorkMode

On Site

Experience Level

Senior

Locations

Bangalore, India

Qualification

Bachelor, Master, Doctoral

Applicants

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