The Job

Memory Layout Design Engineer, Staff

Technology, Data & Digital · Software & Web Development · Frontend · Backend · Full Stack

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In short

Synopsys is seeking a highly experienced Staff Memory Layout Design Engineer to design custom memory IP for various applications. This role involves full layout design ownership, DRC/LVS closure, technology node migrations, and collaboration with circuit designers. The ideal candidate will have a Bachelor's or Master's degree and 8-10 years of relevant experience.

Responsibilities

  • Design and own custom layouts for SRAM, Register Files, ROM, and related memory compiler IP blocks from floorplan through final signoff
  • Execute and close DRC, LVS, ERC, antenna, density, and reliability checks using Virtuoso and physical verification tools
  • Drive technology node migrations for memory compilers, resolving layout and verification issues that emerge with new process rules
  • Collaborate directly with circuit designers to ensure schematic-layout correlation, device matching, symmetry, and design intent are preserved
  • Develop and refine layout methodologies, automation scripts in Tcl, Perl, or Python, and best practices that improve team efficiency and design quality
  • Review layouts created by junior engineers, provide technical guidance, and mentor on complex layout challenges
  • Support customer-specific memory customization projects, working through optimization requests and delivering production-ready IP

Requirements

  • Bachelor's or Master's degree in Electronics, VLSI, Microelectronics, or a related technical field
  • 8 to 10 years of hands-on experience in custom memory layout design, specifically SRAM, Register Files, ROM, or memory compiler development
  • Strong proficiency with custom layout tools such as Cadence Virtuoso or equivalent platforms
  • Demonstrated expertise in DRC/LVS closure, device matching and symmetry, and analog/custom layout techniques
  • Deep understanding of CMOS layout fundamentals, memory architecture, and FinFET technology nodes
  • Experience with parasitic extraction and physical verification flows, and the ability to interpret and act on results
  • Familiarity with scripting in Tcl, Perl, or Python for layout automation is a strong plus

Desired Qualifications

  • You can debug a complex LVS mismatch by tracing through netlists, schematics, and layout views without needing someone to walk you through it
  • You know when to optimize for area and when to prioritize matching or performance, and you can explain the trade-off to a circuit designer in a way that moves the decision forward
  • You review a junior engineer's layout and give feedback that is specific, actionable, and grounded in what will actually cause problems downstream
  • You work across teams with circuit designers, methodology engineers, and CAD without losing sight of what you are trying to deliver or when it needs to be done
  • You stay current on process technology changes and layout challenges that come with new nodes, and you bring that knowledge into your daily work
  • You take ownership of your projects and deliver milestones with limited supervision, raising issues early when dependencies or risks emerge

Benefits

  • Comprehensive medical and healthcare plans that work for you and your family.
  • In addition to company holidays, we have ETO and FTO Programs.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
  • Save for your future with our retirement plans that vary by region and country.
  • Competitive salaries.
#semiconductor#memory compiler#layout design#VLSI#microelectronics
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Company

Synopsys Inc

Job Posted

3 weeks ago

Employment Type

Full Time

WorkMode

On Site

Experience Level

Executive

Locations

Noida, India

Qualification

Bachelor, Master

Applicants

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