Master Thesis: Early Prediction and Optimization of power, Perfomance and Area

Technology, Data & Digital · Software & Web Development · Embedded Systems

In short

This Master Thesis project focuses on using AI to predict and optimize power, performance, and area (PPA) early in the RTL design process. You will work with digital design teams to improve PPA estimation accuracy and provide actionable feedback to designers.

Responsibilities

Work with representative RTL designs and associated simulation, synthesis, power, and implementation data.
Establish PPA baselines and investigate how RTL structures, architectural decisions, and synthesis configurations affect PPA.
Correlate RTL-level characteristics with PPA results after synthesis or physical implementation.
Analyze the PPA impact of common design structures (multipliers, filters, combinational logic, etc.).
Compare alternative RTL or architectural implementations.
Evaluate synthesis configurations and optimization priorities.
Use simulation activity data (VCD, FSDB) to improve power analysis.
Explore data-driven, automated, or AI-assisted methods for identifying PPA optimization opportunities.
Develop a reusable methodology or prototype flow for actionable feedback.
Verify that proposed optimizations preserve functional correctness and satisfy timing/area requirements.

Requirements

Pursuing a Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, Embedded Systems, or a related field.
Knowledge of digital design and computer architecture.
Basic understanding of RTL design using Verilog, SystemVerilog, or VHDL.
Interest in power, performance, and area analysis.
Ability to work methodically with experimental data and evaluate design solutions.
Eagerness to learn about semiconductor design, synthesis, and physical implementation flows.

Desired Qualifications

Experience in logic synthesis or ASIC design flows.
Experience with digital simulation and waveform activity data.
Experience in scripting or programming using Python, Tcl, or a similar language.
Experience in data analysis, machine learning, or AI-assisted engineering methods.

Benefits

Opportunity to help shape the detailed direction of the thesis.
The expected outcome is a systematic and reusable approach for identifying PPA optimization opportunities earlier in the development process.
Improve PPA predictability, reduce manual investigation, and limit iterations between RTL development, synthesis, and physical implementation.

Skills

PythonTclVerilogSystemVerilogVHDLAI

#AI#RTL#PPA#digital design#semiconductor

About Ericsson

Pioneering technology for connecting billions of people worldwide

Our purpose \nTo create connections that make the unimaginable possible.\n\nOur vision\nA world where limitless connectivity improves lives, redefines business and pioneers a sustainable future.\n\nOur values\nPerseverance, professionalism, respect and integrity.\n\nThe future is a place for purpose & vision – ours are clear, and we invite partners, customers and consumers to join us in our journey. \n\nFor a brighter future. For all. Let's #ImaginePossible

See all open jobs at Ericsson Read more about Ericsson Website