Master Thesis: AI-Driven Debug Analysis for ASIC Verification

Technology, Data & Digital · Software & Web Development · Software Engineering · Data Science

In short

This Master's thesis at Ericsson in Lund focuses on applying AI to ASIC verification debug. The student will explore and compare AI-based systems, including agentic approaches, to automate or semi-automate the analysis of simulation data, logs, and other verification artifacts to identify root causes of failures.

Responsibilities

Explore AI-based methods for analyzing ASIC verification failures and identifying likely root causes.
Investigate different control strategies, such as prompt-based workflows, structured analysis steps, tool invocation, iterative reasoning and specialized agents.
Integrate and analyze relevant verification artifacts, which may include simulation logs, waveform derived information, test results, design metadata and other debug data.
Define an evaluation methodology and compare the selected approaches against representative failures.
Assess each approach based on speed, accuracy, resource efficiency, robustness, and usefulness to verification engineers.
Compare the results with a suitable baseline, such as conventional manual debug or a simpler AI-based approach.
Document your findings, limitations and recommendations clearly.

Requirements

Pursuing a master’s degree in electrical engineering, computer engineering, computer science or a related field.
Background in digital design and coding using VHDL, Verilog or SystemVerilog.
Interest in artificial intelligence, automated reasoning or applying AI to engineering workflows.
Strong analytical and problem-solving skills.
Ability to communicate and document technical work clearly.

Desired Qualifications

Knowledge in Computer Science, Electrical Engineering, or a related field.

Skills

VHDLVerilogSystemVerilogAIartificial intelligenceautomated reasoning

#AI#ASIC Verification#Master Thesis#Debug Analysis

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