The Job

Layout Design, Principal Engineer

Technology, Data & Digital · Software & Web Development · Embedded Systems · Software Engineering

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In short

Synopsys is seeking a Principal Engineer specializing in analog and mixed-signal layout design for SERDES IP blocks. This role requires extensive experience, technical leadership, and the ability to optimize layout for signal integrity and reliability in advanced technology nodes. The engineer will collaborate with global teams and contribute to cutting-edge semiconductor solutions.

Responsibilities

  • Design and own analog and mixed-signal layout for SERDES IP blocks including RX, TX, and PLL subcircuits in advanced technology nodes
  • Optimize layout for signal integrity through differential routing, clock and data path management, and parasitic control
  • Implement ESD design constraints and latch-up mitigation across mixed-signal designs
  • Develop custom digital logic cell layout with associated routing to meet performance specifications
  • Execute layout using Custom Compiler and perform verification with ICV, Calibre, Star-RCXT, and PERC
  • Provide technical leadership through layout reviews and mentorship of engineering team members

Requirements

  • MSEE or BSEE with at least 10+ years of related experience in analog and mixed-signal layout design
  • In depth familiarity with layout of analog and mixed-signal CMOS circuits
  • Experience in development of SERDES subcircuit layout including RX, TX, PLL, and related blocks
  • Experience in layout design techniques: optimization for signal integrity including clock and data routes, differential routing, and shielding
  • Implementation of ESD design constraints and latch-up risk mitigation
  • Familiarity with custom digital layout including logic cell layout and associated logic path routing
  • Layout design for reliability including electromigration, IR drop, and related constraints
  • Design to optimize for parasitic layout effects including matching, reliability, and proximity effects
  • Familiarity in design for porting techniques
  • Full custom analog layout design tool experience with Custom Compiler or equivalent
  • Verification tools experience with ICV, Calibre, Star-RCXT, and PERC
  • Experience in working with Jira or Atlassian tools or similar project management platforms
  • Proven understanding of MS Office Suite of applications
  • Exposure to scripting languages including TCL, PERL, or similar

Desired Qualifications

  • You apply technical expertise to resolve complex layout challenges across diverse technology nodes
  • You operate effectively with minimal supervision while maintaining strong collaboration with global engineering teams
  • You contribute technical mentorship that enhances team capabilities and design quality
  • You represent engineering excellence in cross-functional and organizational initiatives

Benefits

  • Comprehensive medical and healthcare plans that work for you and your family.
  • In addition to company holidays, we have ETO and FTO Programs.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
  • Save for your future with our retirement plans that vary by region and country.
  • Competitive salaries.
#Hardware Engineering#Pavia#Italy#Lombardy#Synopsys#Engineering#Employee#Layout Design#Principal Engineer#Mixed-Signal Layout#SERDES#Custom Compiler#ICV#Calibre#Star-RCXT#PERC
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Company

Synopsys Inc

Job Posted

1 month ago

Employment Type

Full Time

WorkMode

On Site

Experience Level

Senior

Locations

Pavia, Italy

Qualification

Bachelor, Master

Applicants

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