Junior SOC Architect
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Qualcomm is looking for a Junior SoC Limits Management Architect to define how next-generation systems balance performance with physical, electrical, and thermal constraints. This role involves bridging hardware IP, system software, and product requirements to create a holistic architecture and guide product definition through early lifecycle stages.
Responsibilities
- Define SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
- Lead cross-functional teams to standardize critical mitigation features across all IP and hardware blocks.
- Drive the long-term evolution of Sensing IPs and trigger mechanisms to address escalating current densities and industry trends.
- Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for mitigation strategies.
- Drive organizational consensus on feature ROI and oversee Post-Silicon Validation to ensure alignment with architectural intent.
- Assist with post-silicon power correlation, matching pre-silicon power models and simulations with actual physical measurements from silicon.
Requirements
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- MS or PhD in Electronics or Computer Engineering, or equivalent with a focus on computer architecture and power/performance analysis.
- 6+ years of ASIC design, verification, validation, integration, or related work experience (5+ years if Master’s; 4+ years if PhD).
- Experience with power management and low-power design methodologies.
- Strong C/C++ development skills for architectural modeling and FW prototyping.
- Strong Python skills for data analysis, performance profiling, and workflow automation.
Benefits
- Competitive annual discretionary bonus program.
- Opportunity for annual RSU grants.
- Highly competitive benefits package designed to support your success at work, at home, and at play.
- Reasonable accommodations to support individuals with disabilities to be able to participate in the hiring process.
- Accessible workplace for individuals with disabilities.
#SoC#Architect#Hardware#ASIC#Power Management#Firmware#Software