Formal Verification CAD Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Qualcomm is looking for a motivated Formal Verification Engineer with over 2 years of experience to join their team in Bangalore. This role involves driving formal verification of complex designs, collaborating with global teams, and enhancing verification methodologies using tools and scripting.

Responsibilities

Drive formal verification of complex design blocks using advanced Formal Apps and robust convergence strategies.
Collaborate with worldwide architecture, design, and systems teams to achieve verification goals.
Review and refine formal setups, proofs, constraints, and abstractions with design/DV teams.
Engage with EDA vendors and evaluate advanced DV methodologies to improve sign‑off quality.
Develop automation scripts (Python preferred) to enhance efficiency and scalability of FV flows.
Analyze challenging formal problems and propose effective verification strategies.
Work with low power formal methodology.

Requirements

2+ years of hands-on experience in Formal Verification.
Strong understanding of formal concepts, proof strategies, and abstraction techniques.
Proficiency with formal tools (Jasper, VC Formal, Questa Formal, etc.).
Excellent scripting skills (Python strongly preferred).
Strong analytical and problem‑solving abilities.
Clear communication skills and ability to collaborate with global teams.
A strong willingness to learn, innovate, and deliver high‑quality results.

Desired Qualifications

Working knowledge of property-based FV (SVA ) is a plus.
Low‑power knowledge is a plus (e.g., power‑aware verification concepts, UPF/CPF, isolation/retention, power/clock gating, power‑aware apps, and basic power‑intent debugging).