The Job

Fabric IP Designer

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

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In short

Microsoft's Compute Silicon & Manufacturing Engineering team is seeking a Fabric IP Designer to develop advanced components of the memory sub-system and contribute to state-of-the-art computer chips. This hybrid role involves RTL coding, timing closure, and collaborating with cross-functional teams to optimize hardware manufacturing and cloud infrastructure.

Responsibilities

  • Be part of a design team developing advanced components of the memory sub-system.
  • Develop automation and AI based solutions to improve organizational efficiency.
  • Own design blocks within complex, coherent fabrics, and bridge IPs.
  • Be responsible for all aspects of the design flow including RTL coding, Lint, CDC, timing closure, etc.
  • Collaborate with team members to define interfaces and make optimal design choices.
  • Work with verification teams to develop test plans and ensure functional correctness.
  • Interface with performance modeling, physical design, design for test, and other teams to optimize tradeoffs.

Requirements

  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.
  • Ability to meet Microsoft, customer and/or government security screening requirements.
  • Microsoft Cloud Background Check required.
  • Must provide proof of US citizenship or US residency/protected status for export control assessment.
  • Verification of citizenship with a valid passport will be required.

Desired Qualifications

  • 5+ years of related technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience or internship experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ year(s) technical engineering experience or internship experience. OR Doctorate degree in Electrical Engineering, Computer Science, Computer Engineering, or related field
  • 3+ years of digital logic design experience for ASIC or FPGA.
  • Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting, etc).
  • Demonstrated proficiency in Computer Architecture, Digital Design, CPU/SoC design principles as part of CPU, SoC and/or IP development.
  • Demonstrated experience and knowledge of design clock crossings and power/UPF.
  • Ability to write scripts using Perl, Tcl, Python etc.
  • Experience using generative AI technologies, agent/skill development.
  • Experience in building and integrating any of the IPs such as protocol bridges, PCIe, cache controllers, memory controllers and DDR, security engines.
  • Experience in building functional fabrics using Coherent and Non-Coherent protocols.
  • Familiarity with Industry standard interface protocols such as AXI or CHI.
  • Familiarity with Synthesis and STA tools.
  • Good verbal and written communication skills.

Benefits

  • The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year.
  • The base pay range in the San Francisco Bay area and New York City metropolitan area is USD $133,800 - $219,200 per year.
  • Certain roles may be eligible for benefits and other compensation.
#Silicon Engineering#Hardware Engineering#ASIC#FPGA#RTL
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Company

Microsoft

Job Posted

1 day ago

Employment Type

Full Time

WorkMode

Hybrid

Experience Level

Mid-Senior

Locations

United States

Qualification

Master, Bachelor, Doctoral

Applicants

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