Experienced Engineer - ASIC Backend Synthesis

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Ericsson is seeking an experienced Physical Synthesis Engineer in Bangalore, India, to join their 5G network development team. The role involves owning the synthesis flow and constraint development for high-performance, low-power SoC designs, working closely with RTL, place-and-route, and DFT teams throughout the chip design cycle. This position offers opportunities for growth and impact in shaping future telecom technologies.

Responsibilities

Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout timing and congestion surprises.
Integrate synthesis with P&R tools for early physical feedback loops, including congestion-aware optimization, placement-aware buffering, and pre-CTS timing.
Collaborate with P&R engineers on DEF/floorplan hand-off and iterate on netlist quality.
Perform flat and hierarchical synthesis for large designs, managing partitioning and interface timing budgets.
Perform formal or equivalence check on the netlist at block or top level.
Track and report key QoR metrics like timing slack, area, cell count, and power.
Identify and resolve synthesis bottlenecks, including critical path restructuring, datapath optimization, and register retiming.
Provide RTL coding guideline feedback to design teams to improve synthesizability and QoR.
Manage technology library characterization inputs (Liberty, LEF, UPF/CPF).
Own synthesis QoR sign-off checklist and contribute to tape-out readiness reviews.
Run block-level and full-chip STA using PrimeTime for timing analysis.
Support MMMC timing closure and analyze timing violations.
Review and validate SDC constraints against post-layout STA results.
Contribute to clock domain crossing (CDC) checks and timing exception audits.

Requirements

5+ years in physical synthesis or logic design implementation
Expert-level use of Fusion Compiler
Strong SDC constraint authoring and management skills
Experience with physical-aware synthesis flows and P&R hand-off
Working knowledge of STA (PrimeTime)
Proficiency in Tcl
Python scripting a strong plus
At least one tape-out on 7nm or below

Desired Qualifications

Familiarity with low-power methodologies (UPF/CPF, multi-Vt, clock gating)
Understanding of PTPX-based power analysis flows
DFT synthesis experience (scan, BIST, boundary scan)
Familiarity with congestion-aware and timing-driven P&R closure

Benefits

Opportunities to advance your skills
Contribute to game-changing 5G/6G technologies
Supportive, innovative environment focused on quality, teamwork, and career development
Lean and Agile principles promoting close collaboration, daily progress-sharing, and continuous improvement

Skills

TclPythonUPFCPFLibertyLEFFusion CompilerPrimeTimeFormality

#5G networks#telecom#ASIC design#digital ASIC#5G/6G technologies

About Ericsson

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