Ethernet Switch ASIC Design Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

The Ethernet Switch ASIC Design Engineer will be responsible for RTL design, synthesis, and timing closure for networking datapath/control logic. This role involves participating in SoC integration, debugging issues, and collaborating with various teams to support chip bring-up.

Responsibilities

Implement RTL design, synthesis, and timing closure for networking datapath/control logic.
Participate in SoC integration with a focus on Ethernet switch subsystems.
Debug functional and performance issues across design, DV, and validation teams.
Collaborate with architecture, firmware, and validation teams to support chip bring-up.

Requirements

Familiarity with ASIC development, including logic design, RTL coding, verification, synthesis, timing closure, and physical design flow.
Familiarity with Ethernet switching concepts such as L2/L3 forwarding, bridging, routing, packet processing pipelines, and basic QoS (queuing, scheduling).
Fluent in Chinese and English (verbal and written).
Ability to work in stressful situations with tight schedules.

Desired Qualifications

Knowledge of AXI/NoC, PCIe, or high-speed interfaces is a plus.
Scripting skills (C/C++, Tcl, Perl) are preferred.
Excellent teamwork, interpersonal, and communication skills.

Benefits

Qualcomm is committed to providing an accessible process for individuals with disabilities.
Qualcomm is committed to making our workplace accessible for individuals with disabilities.