CPU SRAM Design & Layout Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Qualcomm is looking for a CPU SRAM Design & Layout Engineer to join their High Performance CPU Team. The role involves designing, analyzing, and physically realizing high-performance custom SRAMs and register files, collaborating with various engineering teams to optimize for performance, power, area, and reliability.
Responsibilities
- Design and develop custom SRAM and register file circuits optimized for high performance, low power, and scalability.
- Create schematics and perform circuit-level design and optimization.
- Develop memory floorplans and custom layouts based on project requirements and schematics.
- Own memory implementation from initial architecture and floorplanning through physical verification and signoff.
- Perform and oversee layout construction, verification, and optimization.
- Execute and analyze LVS, DRC, ERC, and other physical verification checks.
- Identify and resolve design, verification, and layout issues throughout the development process.
- Perform functional verification, simulation, and margin analysis across process, voltage, and temperature conditions.
- Perform timing, power, and electrical characterization of memory designs.
- Generate and validate all required memory deliverables and collateral models.
- Collaborate with CAD teams to improve modeling, automation, and characterization flows.
- Work with Physical Design teams to resolve memory PPA (Power, Performance, Area) challenges.
- Provide layout guidance and physical implementation recommendations to improve circuit performance, reliability, and manufacturability.
- Contribute to DFT, modeling, automation, and analysis flow development where applicable.
- Develop realistic project schedules and independently drive memory design and implementation activities to completion.
- Provide technical insight and recommendations regarding memory architecture, layout strategy, area optimization, and methodology improvements.
Requirements
- Bachelor's degree in Electrical Engineering or related field with 5+ years of relevant industry experience OR Master's degree in Electrical Engineering with 2+ years of relevant industry experience.
- Experience designing custom SRAM circuits and register files.
- Experience with custom memory layout design and implementation.
- Experience using industry-standard custom design tools and methodologies.
- Experience with circuit simulation, Monte Carlo analysis, and static timing analysis.
- Knowledge of advanced semiconductor technologies, including FinFET and nanosheet process nodes.
- Experience with deep sub-micron layout design for memory, datapath, and standard cell circuits.
- Knowledge of layout floorplanning, hierarchical assembly, and physical verification methodologies.
- Experience with Cadence Virtuoso and Calibre LVS/DRC verification flows.
Desired Qualifications
- Strong understanding of SRAM and register file architectures with advanced custom circuit implementations.
- Strong understanding of high-performance and low-power circuit design techniques.
- Strong knowledge of semiconductor device physics and reliability considerations.
- Experience with variation-aware simulation methodologies in advanced technology nodes.
- Experience with complete memory development flows, including: design entry, functional verification, layout implementation and guidance, simulation and characterization, timing and power analysis, electrical characterization, deliverable model generation.
- Good understanding of the impact of physical implementation on circuit performance, power, and area.
- Experience with memory logical models (Verilog) and functional verification.
- Experience with BIST and DFT methodologies.
- Experience developing memory analysis flows and automation methodologies.
- Knowledge of EMIR analysis and mitigation techniques.
- Proficiency with tools such as NanoTime, Ansys EMIR, ESP-CV, and Liberate.
- Experience writing SKILL code or other automation scripts for layout and design productivity.
- Strong communication and collaboration skills.
Benefits
- Competitive annual discretionary bonus program.
- Opportunity for annual RSU grants.
- Highly competitive benefits package designed to support your success at work, at home, and at play.
- Access to details about US benefits via a link.
#CPU#SRAM#Design#Layout#Engineer#Qualcomm#High Performance CPU Team#Schematic Capture#Circuit Design#Physical Realization#Register Files#CAD#Physical Design#Performance#Power#Area#Reliability#FinFET#Nanosheet#Deep Sub-micron#Floorplanning#Physical Verification#Simulation#Monte Carlo Analysis#Static Timing Analysis#LVS#DRC#ERC#Functional Verification#Characterization#DFT#BIST#EMIR
Company
Qualcomm
Job Posted
2 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
Santa Clara, United States of America
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant