CPU Server Physical Design Timing Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Qualcomm is seeking a CPU Server Physical Design Timing Engineer in Santa Clara, California, to define, develop, and drive CPU timing closure for Oryon CPU Cores. This role involves collaborating with microarchitecture and RTL design teams, coding automation scripts, and working with industry-standard tools and methodologies to meet aggressive power, area, and performance goals.
Responsibilities
- Define, develop, and drive CPU timing closure for Oryon CPU Cores.
- Work with microarchitecture and RTL design teams to develop timing constraints.
- Drive implementation of designs to meet aggressive power, area, and performance goals using industry standard tools/flows.
- Code scripts for STA native tools and enable CPU timing infrastructure and methodology impacting multiple CPU projects.
- Collaborate with Qualcomm central timing technology & methodology team and CPU implementation team.
- STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.
- Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
- Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
- Find root cause of timing miscorrelation and propose solutions.
- Evaluate multiple timing methodologies/tools on different designs and technology nodes.
- Work on automation scripts within STA/PD tools for methodology development.
- Technical writing and Communication skills, willing to work in cross-collaborative environment.
- Strong experience in design automation using TCL/Perl/Python.
- Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
- PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
- Strong experience in design automation using TCL/Perl/Python.
- Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus.
Desired Qualifications
- Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.
- Hands-on experience with STA tools - Prime-time, Tempus.
- Experience in driving timing convergence at Chip-level and Hard-Macro level.
- In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling.
- Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus).
- Expert in scripting languages – TCL, Perl, Python.
- Basic knowledge of device physics.
Benefits
- Competitive annual discretionary bonus program.
- Opportunity for annual RSU grants.
- Highly competitive benefits package designed to support your success at work, at home, and at play.
- Qualcomm is committed to providing an accessible process for individuals with disabilities and making our workplace accessible.
- Reasonable accommodations to support individuals with disabilities to be able to participate in the hiring process.
#CPU#Physical Design#Timing#Engineer#NUVIA#Qualcomm#STA#PPA
Company
Qualcomm
Job Posted
4 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
Santa Clara, United States of America
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant