ASIC Verification Engineer, Staff Level
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
As an ASIC Verification Engineer, Staff Level at Synopsys in Bengaluru, you will be responsible for verifying IP blocks and subsystems, developing and executing verification plans, and building UVM-based verification environments. You will debug complex functional failures, analyze regression results, and collaborate with cross-functional teams to ensure high-quality, customer-ready DesignWare IP.
Responsibilities
- Verify IP blocks and subsystems across DesignWare product lines, developing and executing verification plans, test scenarios, checkers, assertions, and functional coverage models for your assigned areas
- Build and enhance UVM-based verification environments that support block-level and subsystem-level testing, regression automation, and coverage closure
- Debug complex functional failures across IP domains like Ethernet, USB, PCI Express, or other industry-standard protocols, identifying root causes and driving resolution with design and architecture teams
- Analyze regression results, track coverage metrics, and identify gaps or risks that could affect signoff quality or schedule
- Write scripts and automation utilities in Python, Perl, or shell to improve debug efficiency, regression analysis, test development, and coverage closure
- Collaborate with cross-functional teams including design, firmware, quality, and architecture to clarify requirements, resolve technical issues, and align on verification strategy
- Apply AI-assisted techniques where appropriate to accelerate debug workflows, optimize regression cycles, or improve test generation and coverage analysis
Requirements
- Bachelor's or Master's in Electrical, Electronics, or Computer Engineering with 5+ years of hands-on IP or SoC verification experience (or MS with 3+ years)
- Strong proficiency in SystemVerilog and UVM, VMM, or OVM methodologies, with real project experience developing verification environments, test plans, checkers, assertions, and functional coverage
- Hands-on experience with industry-standard simulators such as VCS and associated debug tools, including waveform analysis and regression infrastructure
- Demonstrated ability to debug complex functional failures, analyze regression results, track issues to closure, and support verification signoff activities
- Experience writing scripts or automation utilities in Python, Perl, or shell to improve verification productivity, debug efficiency, or regression analysis
- Practical understanding of verification planning, coverage analysis, quality criteria, and what it takes to reach signoff on real IP or SoC projects
Desired Qualifications
- Experience with DesignWare IP or similar synthesizable IP verification projects is a strong plus
- Familiarity with protocols such as Ethernet, USB, or PCI Express
- Exposure to AI-assisted methods for debug, regression optimization, test generation, or coverage closure is desirable
Benefits
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement plans
- Competitive salaries
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Company
Synopsys Inc
Job Posted
1 hour ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bengaluru, India
Qualification
Bachelor, Master
Applicants
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