ASIC Physical Design, Principal Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys seeks a Principal Engineer for ASIC Physical Design, focusing on SerDes IP. The role involves owning physical integration, timing closure, and power optimization at advanced FinFET nodes. Requires extensive experience in RTL to GDSII flows and customer engagement.
Responsibilities
- Own physical integration for advanced SerDes IP from floorplanning through GDSII, including timing closure, power optimization, and signoff at 16nm and below
- Drive RTL-to-GDSII flows for 56G, 112G, and 224G PAM4/6 SerDes across FinFET nodes, working closely with front-end, analog, and CAD teams to resolve integration challenges
- Develop and validate timing constraints, clock architectures, and low-power design techniques that meet customer PPA targets and enable first-pass silicon success
- Lead customer engagements on physical integration topics, including SOC-level integration planning, constraint delivery, and tapeout support
- Build and improve design methodologies, automation scripts (Perl, Tcl, Python), and flows that reduce customer effort and improve delivery predictability
- Debug and resolve complex analog-digital interface issues in collaboration with analog design and verification teams
- Mentor engineers across the team on physical design best practices, timing closure strategies, and advanced node challenges
Requirements
- MSEE with 10+ years or BSEE with 12+ years of digital or physical design experience, with recent contributions to project tapeouts
- Deep hands-on experience with the full RTL-to-GDSII flow, including chip-level integration, timing closure, and physical signoff
- Proven experience with advanced FinFET nodes (TSMC 16nm or below), including low-power design techniques and process-specific challenges
- Strong understanding of timing constraint development, clock architecture, and design techniques required to meet power and area targets
- Experience leading technical initiatives or projects, with a track record of driving decisions and delivering results on schedule
- Solid understanding of digital and mixed-signal verification flows, SOC integration challenges, and analog-digital interface considerations
- Strong scripting and automation skills in Perl, Tcl, or Python, with a methodology-driven approach to design and CAD flows
Desired Qualifications
- Ability to walk into a customer meeting three weeks before tapeout, understand their integration issue in fifteen minutes, and give them a path forward that actually works
- Willingness to make decisions with incomplete information and own the call
- Skill in identifying whether a timing problem is a constraint problem, a floorplan problem, or an architecture problem
- Comfort pushing back when a plan does not make sense
- Ability to explain complex physical design tradeoffs to different stakeholders
- Comfort with international travel when customer engagements or team collaboration require it
Benefits
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- ESPP with a 15% discount and 24-month look-back
- Retirement plans
- Competitive salaries
- Annual bonus, equity, and other discretionary bonuses
- Comprehensive health, wellness, and financial benefits
Skills
RTLtiming closurepower optimizationGDSIIPerlTclPythonanalog-digital interface
#semiconductor#ASIC#SerDes#physical design#engineering#IP
About Synopsys Inc
Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…
Company
Synopsys IncJob Posted
1 day ago
Employment Type
Full Time
Work mode
On Site
Salary
US$197,800–296,700 / year
Experience Level
Executive
Locations
Sunnyvale, United States
Qualification
Master, Bachelor
Applicants
Be an early applicant
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