ASIC Logic Design Verification Principal Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Synopsys is looking for a Principal Engineer in ASIC Logic Design Verification with over a decade of experience. This role involves architecting UVM environments, writing System Verilog test sequences, and mentoring junior engineers to ensure the delivery of high-quality, verified interface IP designs.
Responsibilities
- Collaborate with design teams to define verification requirements and translate specs into test plans.
- Architect and implement UVM testbench environments.
- Write System Verilog test sequences and constrained random stimulus.
- Implement System Verilog Assertions for functional and formal verification flows.
- Build and analyze functional and code coverage metrics.
- Lead and mentor a team of verification engineers.
Requirements
- Bachelor's or master’s degree in computer engineering, Electrical Engineering, or Communication Engineering.
- 12+ years of hands-on ASIC design verification experience with strong focus on UVM-based functional verification.
- Deep expertise in System Verilog, including advanced testbench architecture, constrained random verification, and coverage-driven verification.
- Proven experience implementing System Verilog Assertions for functional and formal verification flows.
- Strong programming skills in at least two of: C, System Verilog, TCL, Perl, or Python.
Desired Qualifications
- Experience with PCI Express and CXL protocols is a strong plus.
- Experience in interface IP verification, formal verification tools like Jasper or VC Formal, and AI-assisted coding tools like Cursor or GitHub Copilot will set you apart.
- Ability to spot verification gaps and articulate their importance.
- Precision and respect in code reviews.
- Proactive approach to work with available information.
- Natural ability to teach and explain complex concepts.
Benefits
- Comprehensive medical and healthcare plans.
- ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- Purchase Synopsys common stock at a 15% discount.
- Retirement plans.
- Competitive salaries.
#ASIC#Logic Design#Verification#Principal Engineer#Semiconductor#Hardware Engineering#Chip Architecture#Circuit Design#UVM#System Verilog#PCI Express#CXL
Company
Synopsys Inc
Job Posted
1 week ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Executive
Locations
Dublin, Ireland
Qualification
Bachelor, Master
Applicants
Be an early applicant