ASIC Digital Design , Sr Staff Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Synopsys is seeking an experienced ASIC Digital Design Sr Staff Engineer in Bengaluru, India to design and develop cutting-edge semiconductor solutions. The role involves creating RTL for high-speed Ethernet IP cores, translating protocol specifications into micro-architectures, and driving timing analysis and closure for complex designs.
Responsibilities
- Design and code RTL for high-speed Ethernet IP cores ranging from 100G to 1.6T, focusing on low latency and timing closure in complex datapath and control logic.
- Translate protocol specifications and functional requirements into micro-architecture and detailed design documents for DesignWare IP in Ethernet, AMBA AXI, CHI, PCIe, USB, MIPI, or memory controller domains.
- Build and refine directed Verilog testbenches to improve functional and code coverage, analyzing metrics and defining targeted test cases that catch real bugs.
- Perform technical reviews of functional specs, micro-architecture documents, and RTL code from peers across global design teams.
- Drive timing analysis and closure for high-speed designs using synthesis, STA, lint, CDC, and formal verification flows.
- Apply low power design methodologies and automotive safety requirements to IP development.
- Collaborate with verification, integration, and product teams across Bangalore, the US, and other global sites to deliver production-quality IP on schedule.
Requirements
- Bachelor's in Electrical Engineering with 8+ years of hands-on ASIC or IP design experience, or Master's with 6+ years.
- Deep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers.
- Strong working knowledge of at least one protocol from this list: AMBA (AHB, AXI, CHI), SD, eMMC, DDR, PCIe, USB, MIPI. High-speed Ethernet (100G and above) experience is a strong plus.
- Proven ability to create micro-architecture and detailed design documents from functional specs for small to medium complexity blocks, especially control-path designs like async FIFOs, DMA engines, or SRAM/DPRAM interfaces.
- Hands-on experience with Verilog or SystemVerilog, simulation tools, synthesis flows, static timing analysis, lint, CDC, and formal verification tools.
- Solid understanding of high-speed, low-latency design techniques and timing closure challenges. Experience with datapath designs or arithmetic algorithms like FEC is a plus.
- Familiarity with Perforce or similar version control systems, and scripting in Perl or shell for automation.
Desired Qualifications
- You can take a vague feature request and turn it into a clean, implementable design without needing three rounds of clarification meetings.
- When you review RTL, you catch the subtle issues that would have caused problems in integration, and you explain them clearly enough that the engineer learns something.
- You know how to prioritize when you are juggling timing closure, coverage improvements, and a design review scheduled for tomorrow, and nothing falls through the cracks.
- You communicate technical tradeoffs in writing and in review meetings with enough clarity that engineers in other timezones can act on your feedback without a follow-up call.
- You push back when a spec is ambiguous or a schedule does not account for real design complexity, and you do it in a way that moves the conversation forward.
- You treat documentation as part of the design, not an afterthought, because you know the next person reading your micro-arch doc might be you in six months.
Benefits
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.
#ASIC#Digital Design#Engineer#RTL#IP Cores#Ethernet#Datapath#Control Logic#Micro-architecture#DesignWare#Verification#Synthesis#Static Timing Analysis#Lint#CDC#Formal Verification#Low Power Design#Automotive Safety#SoC#Data Center#AI
Company
Synopsys Inc
Job Posted
1 month ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bengaluru, India
Qualification
Bachelor
Applicants
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