ASIC Digital Design, Sr Staff Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Synopsys seeks a Sr Staff ASIC Digital Design Engineer in Dublin, Ireland, to lead verification efforts for semiconductor solutions. The role requires extensive experience in UVM and System Verilog, focusing on architecting testbenches and ensuring silicon reliability to drive innovation.

Responsibilities

Collaborate with design teams to define verification requirements and translate specs into test plans.
Architect and implement UVM testbench environments, including agents, scoreboards, and reusable verification components.
Write System Verilog test sequences and constrained random stimulus to stress designs.
Implement System Verilog Assertions for simulation-based functional verification and formal verification flows.
Build and analyze functional and code coverage metrics, identify gaps, and drive coverage closure.
Lead and mentor a team of verification engineers on UVM methodology and best practices.

Requirements

Bachelor's or master’s degree in computer engineering, Electrical Engineering, or Communication Engineering.
8+ years of hands-on ASIC design verification experience with a strong focus on UVM-based functional verification.
Deep expertise in System Verilog, including advanced testbench architecture, constrained random verification, and coverage-driven verification.
Proven experience implementing System Verilog Assertions for functional and formal verification flows.
Strong programming skills in at least two of: C, System Verilog, TCL, Perl, or Python.
Experience with PCI Express and CXL protocols is a strong plus.
Experience in interface IP verification, formal verification tools like Jasper or VC Formal, and AI-assisted coding tools like Cursor or GitHub Copilot will set you apart.

Desired Qualifications

Ability to spot verification gaps and articulate their importance.
Precision and respect in code reviews.
Proactive approach to building with incomplete information.
Natural teaching ability for complex verification concepts.

Benefits

Competitive salaries.
Comprehensive medical and healthcare plans.
ETO and FTO Programs for Time Away.
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
ESPP with a 15% discount on Synopsys common stock.
Retirement Plans (vary by region and country).

Skills

UVMSystem VerilogTCLPerlPythonC

#asic#digital design#verification#engineer

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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