ASIC Digital Design, Sr Staff Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is hiring a Sr Staff Engineer in Yerevan, Armenia, for ASIC digital design. The role involves designing and optimizing complex semiconductor IP, collaborating with cross-functional teams, and contributing to advanced process nodes. Requires 8+ years of experience with Verilog, Python, Tcl, Perl, and deep knowledge of synthesis and timing analysis.
Responsibilities
- Design RTL modules for UCIe Controller IP from microarchitecture through synthesis-ready implementation
- Optimize designs to meet timing, power, and area targets across multiple process nodes
- Develop Python/tcl/perl automation for design generation and flow integration
- Collaborate with cross-functional teams to resolve timing and power challenges
- Contribute to design reviews and methodology development
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
- 8+ years of ASIC digital design experience with RTL ownership in production silicon
- Expert Verilog proficiency for timing-critical designs
- Strong Python/Tcl/Perl scripting skills for design automation
- Deep knowledge of synthesis, timing analysis, and power optimization
Desired Qualifications
- Experience with Controller IP or high-speed interfaces is preferred
- Understand how RTL structure affects timing and power outcomes
- Communicate effectively across technical disciplines
- Produce maintainable code that supports collaboration
- Identify process improvements proactively
- Resolve technical issues through systematic analysis
Benefits
- Comprehensive medical and healthcare plans
- ETO and FTO Programs for time away
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement plans that vary by region and country
- Competitive salaries
#ASIC#Digital Design#RTL#semiconductor#IP#timing closure#power optimization#process nodes#Python#Tcl#Perl#synthesis#timing analysis#HPC#automotive#AI
Company
Synopsys Inc
Job Posted
3 days ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Yerevan, Armenia
Qualification
Bachelor, Master
Applicants
Be an early applicant