ASIC Digital Design Senior Manager
In short
Synopsys is hiring an ASIC Digital Design Senior Manager in Bengaluru, India to lead the LPDDR PHY IP team. This role involves managing design engineers, contributing to all design phases, and ensuring high-performance, low-power products. Requires a BS in Electrical Engineering with significant experience in complex technical development and people management.
Responsibilities
- Manage a team of design engineers and work with Architect, Verification, Physical implementation, and Firmware teams.
- Contribute to all phases of designs of DDR PHY IP from design specification to productization.
- Provide customer support for their SoCs.
- Lead the team to deliver the design and achieve the best timing, performance, and power goals.
Requirements
- BS in Electrical Engineering with at least 12-15 years of experience in complex technical development.
- 2 years of experience in people management, developing employees.
- Experience with synthesizable Verilog and System Verilog design concepts and implementation.
- Experience with front-end design flows including linting, synthesis, STA, cross-domain clocking, DFT, and power optimization techniques.
- Exhibit excellent communication skills and be self-motivated.
Desired Qualifications
- Understanding of memory and memory PHY architecture is a plus.
Benefits
- Comprehensive medical and healthcare plans.
- ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Retirement plans that vary by region and country.
- Competitive salaries.
#ASIC#Digital Design#Semiconductor#IP#LPDDR#PHY
Company
Synopsys Inc
Job Posted
2 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bengaluru, India
Qualification
Bachelor
Applicants
Be an early applicant