AICS Design Verification Engineer- Multiple levels

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Qualcomm is seeking an AICS Design Verification Engineer for multiple levels in Vancouver, BC. This role involves comprehensive pre-silicon test planning, testbench development using SystemVerilog-UVM, and formal verification for digital power IPs. The position requires a Bachelor's degree and 2+ years of experience, with Master's/PhD degrees and more extensive experience being preferred.

Responsibilities

Responsible for comprehensive pre-silicon test planning for digital power IPs.
Develop testbench using advanced verification methodologies such as SystemVerilog-UVM.
Develop coverage and assertion models.
Perform formal verification, including property checking.
Learn and deploy power-aware UPF verification flow and methodology.
Involve in developing automation to improve verification efficiency.

Requirements

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field.
2+ years of experience with ASIC design and verification tools, techniques, and methodology.

Desired Qualifications

Master’s degree in Computer Science, Electrical Engineer, Computer Engineering, or a closely related field.
6+ years of experience with ASIC design and verification tools, techniques, and methodology.
6+ years of experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL.
6+ years of experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills.
6+ years of experience with developing block-level testbench environment using SystemVerilog.
6+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification.
6+ years of experience with scripting/automation skills using either Perl or python.
Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable (not mandatory).
Knowledge or experience with Assertion Based Formal Verification is desirable (not mandatory).

Benefits

Competitive annual discretionary bonus program.
Opportunity for annual RSU grants.
Highly competitive benefits package designed to support your success at work, at home, and at play.

Skills

SystemVerilogUVMVerilogVHDLC++CPerlpythonAXIAHBAPB

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