Advanced Package Design Engineer – Principal Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Wir suchen einen Principal Engineer zur Leitung eines 2.5D/3D Advanced Package Design-Teams, das die nächste Generation von Hochleistungsrechnern (HPC) und Rechenzentrumsprodukten unterstützt. Diese Führungskraft ist verantwortlich für die Entwicklung, Bereitstellung und kontinuierliche Verbesserung skalierbarer 2.5D/3D-Paketentwurfsmethoden und -abläufe.
Responsibilities
- Build, manage, mentor, and grow a high-performing 2.5D/3D advanced package design team.
- Own the strategy, roadmap, architecture, implementation, qualification, and deployment of end-to-end 2.5D/3D package design methodologies and flows.
- Develop standardized, scalable, and reusable flows spanning early package planning, die/chiplet assembly definition, floorplanning, HBM and chiplet placement, bump and interface planning, interposer/bridge design, substrate design, package verification, signoff, tapeout, and release.
- Lead implementation of 2.5D/3D packages using silicon interposers, silicon bridges, RDL interposers, advanced organic substrates, hybrid-bonded or vertically stacked die, HBM, and other emerging integration technologies.
- Evaluate and deploy foundry and EDA-vendor 3DIC solutions, including TSMC 3Dblox-compatible methodologies.
- Define tool requirements and drive technical alignment with Cadence, Siemens EDA, Synopsys, Ansys, foundries, and other ecosystem partners.
- Establish design-flow architecture, data models, interfaces, automation frameworks, configuration management, regression testing, release management, metrics, documentation, and user support.
- Guide package architecture and physical implementation across die/chiplet floorplanning, bump maps, HBM placement, die-to-die interfaces, package connectivity, routing topology, layer-stack optimization, power/ground distribution, board escape, and package-size optimization.
- Define and govern package verification and signoff requirements.
- Partner with silicon architecture, SoC physical design, DFT, SI/PI, thermal, mechanical, board, product engineering, manufacturing, and supply-chain teams.
- Lead package design execution from feasibility through tapeout and production release.
- Drive methodology correlation and validation using representative test cases and product designs.
- Engage foundries, OSATs, substrate suppliers, and assembly partners.
- Develop team capability plans, hiring profiles, training, succession plans, and technical career paths.
- Represent advanced package design in executive and program reviews.
Requirements
- Proven experience building and leading advanced package design, 3DIC methodology, package CAD, or physical-design teams.
- Deep knowledge of 2.5D/3D integration technologies and structures, including silicon interposers, silicon bridges, RDL interposers, advanced organic substrates, HBM integration, chiplets, die stacking, micro-bumps, hybrid bonding, and package assembly.
- Hands-on experience defining or deploying production 2.5D/3D design flows covering planning, implementation, verification, multi-physics analysis, design-data handoff, tapeout, and release.
- Understanding of industry 3DIC EDA ecosystems and foundry design enablement, including TSMC 3Dblox concepts.
- Expertise with relevant package and 3DIC implementation environments from Cadence, Siemens EDA, Synopsys, or equivalent vendors.
- Expert knowledge of advanced package physical design, including multi-die floorplanning, HBM placement, bump and interface planning, pinout optimization, high-density routing, interposer/bridge implementation, substrate stackup, power/ground planning, and board escape.
- Strong understanding of package-level SI/PI and electromagnetic effects for HBM, UCIe and other die-to-die interfaces, PCIe, DDR, high-speed SerDes, clocks, and high-current power delivery.
- Working knowledge of package thermal-mechanical and reliability analysis.
- Experience establishing DRC, DFM, ERC, connectivity, extraction, multi-physics, and release-signoff methodology.
- Strong scripting and automation mindset, with experience developing maintainable flows using languages and environments such as Python, Tcl, Perl, shell, APIs, workflow orchestration, regression systems, and version control.
- Ability to assess EDA tool capability, benchmark competing solutions, define requirements, drive vendor roadmaps, resolve tool and methodology gaps, and establish production-support models.
- Excellent executive communication, technical decision-making, cross-functional influence, supplier engagement, and ability to lead globally distributed teams.
Desired Qualifications
- Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, Mechanical Engineering, Materials Science, or a related field, with 15+ years of semiconductor package design, 3DIC, physical-design methodology, or related experience.
- Demonstrated record of building and managing a substantial advanced package design or methodology organization.
- Proven ownership of production 2.5D/3D package design methodology and implementation for AI, HPC, Datacenter, accelerator, networking, or other high-performance multi-die products.
- Direct experience delivering packages that integrate compute SoCs or chiplets with HBM using silicon-interposer, silicon-bridge, RDL-interposer, or vertically integrated 3D solutions.
- Experience integrating foundry reference flows and assembly-description frameworks such as TSMC 3Dblox into internal design, analysis, verification, and tapeout environments.
- Extensive experience with industry-leading 2.5D/3D IC design, implementation, and verification environments, including Cadence Innovus, Integrity 3D-IC, Allegro Package Designer (APD), Virtuoso, Siemens Calibre 3DSTACK, and comparable Synopsys and Ansys 3DIC solutions.
- Demonstrated experience evaluating, integrating, and deploying multi-vendor EDA tools within foundry-qualified 2.5D/3D design flows.
- Experience establishing cross-domain chip-package-board co-design and multi-physics workflows.
- Experience working directly with leading foundries, OSATs, substrate suppliers, assembly partners, EDA vendors, and IP providers.
- Understanding of HBM, UCIe or other die-to-die protocols, PCIe, DDR, and high-speed SerDes.
- Demonstrated ability to define methodology roadmaps, prioritize investments, establish measurable design-flow quality and productivity targets, and drive deployment across a global engineering organization.
- Demonstrated innovation through advanced package solutions, EDA methodologies, automation, patents, publications, industry working groups, or standards engagement is highly desirable.
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package designed to support your success at work, at home, and at play.
Skills
PythonTclPerlShell scriptingCadenceSiemens EDASynopsysAnsysHBMUCIePCIeDDR
#2.5D#3D#HPC#Datacenter#Package Design#Semiconductor#Chiplet
About Qualcomm
Enabling a world where everyone and everything can be intelligently connected.
Enabling a world where everyone and everything can be intelligently connected.\n\n
Company
QualcommJob Posted
1 day ago
Employment Type
Full Time
Work mode
On Site
Salary
US$210,000–315,000 / year
Experience Level
Senior
Locations
San Diego, United States of America
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant