The Job

Principal Design Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

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In short

Microsoft is seeking a Principal Design Engineer for its Artificial Intelligence System on Chip (AISoC) Silicon team. This role involves driving high-performance designs, including microarchitecture specification, RTL design, synthesis, and SOC integration, while collaborating with various engineering teams.

Responsibilities

  • Drive high performance, high bandwidth designs.
  • Work on Intellectual Property (IP) microarchitecture specification.
  • Perform Register Transfer Level (RTL) design.
  • Engage in synthesis and System on Chip (SOC) integration on different subsystems.
  • Interact with architecture, verification, and physical design teams.

Requirements

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
  • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience.
  • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience.
  • OR equivalent experience.
  • Ability to meet Microsoft, customer and/or government security screening requirements.
  • Requirement to pass Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
  • Requirement to provide proof of citizenship or US residency for assessment of eligibility to access export-controlled information.

Desired Qualifications

  • 12+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/Lint closure.
  • 10+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs.
  • 8+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug.
  • 8+ experience in Designing Fabric/Network On Chip or Networking ASICs or Complex Control Logic.
  • D2D IP design experience.
  • Fabric design experience.
  • CPU and/or graphics core design experience.
  • Complex algorithmic designs for AI usages experience.
  • Script development experience.

Benefits

  • Base pay range for this role across the U.S. is USD $142,800 - $274,800 per year.
  • Base pay range for this role in San Francisco Bay area and New York City metropolitan area is USD $188,000 - $304,200 per year.
  • Certain roles may be eligible for benefits and other compensation.
#Silicon#Hardware Engineering#Cloud Infrastructure#AI#SOC
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Company

Microsoft

Job Posted

1 week ago

Employment Type

Full Time

WorkMode

Hybrid

Experience Level

Executive

Locations

United States

Qualification

Doctoral, Master, Bachelor

Applicants

Be an early applicant