Infra Design Verification Staff Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Qualcomm seeks an Infra Design Verification Staff Engineer in Bangalore, India, to work on DDR Subsystem verification. Responsibilities include creating DV infrastructure, integrating VIPs, executing test plans, and ensuring high-quality verification for cutting-edge products.
Responsibilities
- Create DV infrastructure for verification
- Integrate VIP's
- Create and execute test plans
- Debug failures
- Write assertions
- Close code and functional coverage
- Ensure high quality verification
- Work with all stakeholders to ensure program success
Requirements
- Bachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field.
- 5+ years Hardware Engineering experience or related work experience.
- Strong Debug skills
- Strong UVM skills
- Strong System Verilog skills
- Understanding Specs and Standards and developing relevant test plans
- Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved
- Comfortable checking builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug
- Willingness to dig into fail and understand what is happening
- 5+ Years of industry experiences in the following areas:
- Thorough understanding of Digital design concepts
- Thorough understanding dv methodologies and tools
- Good understanding of LPDDR4/LPDDR5 protocols
- Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite
Benefits
- Qualcomm is an equal opportunity employer.
- Qualcomm is committed to providing an accessible process.
- Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.
- Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
#Hardware Engineering#Design Verification#DDR Subsystem#Infra IP