Staff Engineer – Synthesized Model IP Design
Technology, Data & Digital · Software & Web Development · Embedded Systems · Software Engineering
In short
We are looking for a Staff Engineer with over 10 years of experience in ASIC/SoC design to create synthesized IP models for emulation and FPGA prototyping. This role involves technical leadership in RTL design, C/C++ modeling, FPGA implementation, and emulation technologies, requiring collaboration across multiple engineering teams.
Responsibilities
- Lead design and development of synthesizable IP models for emulation and FPGA prototyping.
- Contribute to architecture, micro-architecture definition, design reviews, and implementation strategies.
- Develop and optimize RTL implementations using Verilog/SystemVerilog focusing on functionality, performance, area, and timing.
- Develop and maintain C/C++ reference models aligned with RTL implementations.
- Drive IP integration, debug, validation, and bring-up across simulation, emulation, and FPGA.
- Support FPGA implementation (synthesis, timing closure, hardware validation, optimization).
- Collaborate with architecture, verification, software, and system teams for platform bring-up and software development.
- Prepare project plans, estimate schedules, identify technical risks, and drive execution.
- Mentor 2-4 engineers, providing technical guidance and conducting code reviews.
- Drive adoption of automation, AI-assisted design, and productivity improvements.
Requirements
- Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering, or related field.
- 10+ years of experience in ASIC, SoC, FPGA, RTL design, or emulation/prototyping.
- Experience delivering complex IP, subsystem, or SoC projects from development through validation.
- Strong expertise in synthesizable model development, Verilog/System Verilog RTL design, and ASIC/SoC design methodologies.
- Experience translating specifications into high-quality RTL.
- Strong C/C++ programming skills for reference models and validation frameworks.
- Good understanding of AXI/AHB/APB protocols, CDC, reset architecture, power management, and system-level integration.
- Experience with Git, CI/CD workflows, and scripting (Python, Tcl, Perl, Shell).
- Hands-on experience with Xilinx FPGA design and prototyping (UltraScale+, Versal).
- Experience with Vivado tools for FPGA synthesis, implementation, timing closure, debug, and hardware bring-up.
- Familiarity with emulation platforms (Siemens Veloce/Veloce TBX, Cadence Zebu, Palladium).
- Understanding of SCE-MI, DPI-C, transactors, transaction-based acceleration, software-driven validation, and co-emulation.
- Familiarity with LPDDR5/LPDDR5X/LPDDR6, PCIe, Ethernet, USB, UART, I2C/I3C, MIPI C-PHY/D-PHY, AXI, AHB, and APB protocols.
- Strong analytical and problem-solving skills.
- Excellent communication and collaboration skills.
- Experience mentoring junior engineers and leading technical discussions.
- Ability to plan, prioritize, and execute projects with ownership.
- Self-motivated with a focus on engineering excellence and innovation.
Desired Qualifications
- Experience with large-scale SoC prototyping, software bring-up, and emulation-based validation.
- Experience with multi-FPGA partitioning and system integration.
- Familiarity with AI-assisted semiconductor design methodologies and productivity tools.
- Exposure to HLS methodologies and cloud-based EDA workflows.
Benefits
- Equal opportunity employer.
- Commitment to providing accessible processes for individuals with disabilities.
- Reasonable accommodations available for individuals with disabilities.
- Opportunity to work with leading-edge technology in a global company.
#Staff Engineer#Synthesized Model IP Design#ASIC#SoC#FPGA#Emulation#RTL Design#Hardware Engineering
Company
Qualcomm
Job Posted
3 days ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bengaluru, India
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant