The Job

Sr. Staff/Principal PCIE Subsystem Architect

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

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In short

Qualcomm is looking for a Sr. Staff/Principal PCIe Subsystem Architect with deep expertise in high-speed interfaces like PCIe, CXL, UCIe, NVMe, and Ethernet for next-generation AI datacenter products. The role involves defining subsystem architecture, driving requirements, and ensuring system-level performance and reliability. This is an on-site position in Santa Clara, California.

Responsibilities

  • Define subsystem architecture and drive requirements from accelerator card and server level through full-rack scale-up and scale-out deployments.
  • In-depth knowledge of PCIe, Ethernet, and other high-speed I/O interfaces used in datacenter and accelerator products.
  • Strong understanding of PCIe ordering models, producer-consumer ordering, ARM ordering behavior, DMA flows, and high-speed serial interface behavior.
  • Strong understanding of PCIe Gen6/Gen7 requirements, including FLIT mode, PAM4 signaling implications, link training, latency, error handling, and system-level tradeoffs.
  • Experience with PCIe error containment and recovery mechanisms such as AER, DPC, CRS, FLR, and reset separation.
  • Experience with I/O virtualization and isolation technologies such as SR-IOV, SIOV, PF/VF isolation, and related software-visible requirements.
  • Strong understanding of RAS, telemetry, reliability, and security requirements for server-class SoCs and accelerator subsystems.
  • Good knowledge of scale-up and scale-out architectures, including PCIe switch fabrics, NIC connectivity, host-to-accelerator orchestration, and rack-level deployment considerations.
  • Ability to work effectively in a high-caliber, international, multi-site engineering team.

Requirements

  • Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
  • OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
  • OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
  • Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field and 10+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
  • OR Master’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field and 8+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
  • OR PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related field and 6+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
  • 3+ years of experience with high-performance designs involving PCIe, Ethernet, or other high-speed I/O interfaces.

Desired Qualifications

  • Good understanding of PCIe integrity, security, and confidential-compute features such as IDE, DOE/SPDM, TDISP, SR-IOV, and SIOV.
  • Strong familiarity with PCIe CEM standards, add-in card deployment constraints, retimers, signal-integrity considerations, and system-level validation flows.
  • Good understanding of emerging AI interconnect standards and ecosystems such as UCIe, UALink/UAL, and UEC.
  • Good understanding of PCIe firmware, BIOS/UEFI, operating-system, driver, and system-software requirements.
  • Good understanding of high-speed SerDes and PHY technologies, including PCIe PHY, Ethernet PHY, PAM4 signaling, and power/performance tradeoffs.
  • Good knowledge of server SoC architectures with emphasis on security, RAS, virtualization, IOMMU/SMMU, DMA, address translation, and telemetry.
  • Ability to engage with customers, product management, systems teams, and cross-functional architecture stakeholders to gather requirements and drive technical alignment.
  • Excellent written and verbal communication skills, with the ability to create architecture specifications, requirement documents, and executive-level technical summaries.

Benefits

  • Competitive annual discretionary bonus program
  • Opportunity for annual RSU grants
  • Highly competitive benefits package designed to support your success at work, at home, and at play.
  • Details about US benefits available at a link.
#ASICS#datacenter#AI#PCIe#CXL#UCIe#NVMe#Ethernet#high-speed interfaces#architecture
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Company

Qualcomm

Job Posted

3 weeks ago

Employment Type

Full Time

WorkMode

On Site

Experience Level

Senior

Locations

Santa Clara, United States of America

Qualification

Bachelor, Master, Doctoral

Applicants

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