SoC Verification Staff Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing
In short
Synopsys is looking for a Staff Engineer with extensive experience in SoC verification, specializing in System Verilog and UVM. The role involves defining verification plans, building testbenches, debugging failures, and collaborating with design teams to ensure the reliability of cutting-edge semiconductor solutions. This position is based in Ho Chi Minh City, Vietnam.
Responsibilities
- Define block and subsystem verification plans that map directly to design specifications and protocol requirements
- Build UVM testbenches in System Verilog, including agents, scoreboards, coverage models, and assertion monitors
- Write constrained random and directed tests that exercise protocol compliance, corner cases, and error injection scenarios
- Debug RTL and testbench failures using simulators and waveform analysis to root cause and resolve issues
- Collaborate with RTL designers and global verification engineers to align on design intent and coverage goals
- Apply formal verification techniques to prove properties and close coverage gaps
- Drive verification closure by tracking coverage metrics and iterating on test plans until signoff
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
- 6+ years of hands-on design verification experience in the semiconductor industry
- Strong proficiency in System Verilog and UVM for building testbenches and implementing coverage
- Working knowledge of at least one protocol such as AMBA, PCI Express, CXL, UCIe, Ethernet, HBM, or DDR
- Experience with industry standard simulators like VCS, Xcelium, or Questa, and version control systems
- Solid scripting skills in Python, Perl, or Tcl for automation and regression management
Desired Qualifications
- You can take a protocol spec and translate it into a verification plan that covers what matters, not just what is easy to test
- When a regression fails before a milestone, you dig into the waveform and find the root cause instead of waiting for triage
- You communicate clearly with RTL designers about what you found and what needs to change, without blame
- You manage multiple verification tasks in parallel without losing track of coverage goals or debug priorities
- You ask questions when something in the design does not make sense, and you do not assume someone else will catch it
Benefits
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement plans
- Competitive salaries
#Engineering#SoC Verification#Staff Engineer#Semiconductor#Hardware Engineering#Chip Architecture#Circuit Design#ASIC Verification#IP Verification#Design Verification#Digital Verification
Company
Synopsys Inc
Job Posted
4 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Ho Chi Minh City, Vietnam
Qualification
Bachelor, Master
Applicants
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