Silicon SoC Analog Integration Lead, Google Cloud
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
As the SoC Analog Integration Lead for Google Cloud in Bengaluru, you will drive the strategy, selection, and integration of high-speed analog and mixed-signal IPs into complex SoCs. This role requires a Bachelor's degree in Electrical Engineering or related field, 10 years of experience with IPs like PCIe, SerDes, HBM, or DDR PHYs, and expertise in managing IP vendors and post-silicon validation.
Responsibilities
- Lead the evaluation and selection of third-party analog/mixed-signal IPs (e.g., PCIe, SerDes, HBM PHY), establishing detailed technical SLAs, functional specifications, and delivery schedules.
- Serve as the primary technical interface to IP vendors, overseeing technical reviews, bug tracking, silicon errata evaluations, and waiver processes.
- Collaborate with floorplan and physical design teams to define integration requirements, ensuring alignment on placement, power delivery, clocking, and functional interfaces.
- Partner with packaging, PCB, and SI teams to optimize high-speed trace and power delivery, driving the die-package co-design process.
- Oversee AMS simulations and netlist checks, while leading post-silicon bring-up, lab characterization (BER, jitter), and validation to support the product ramp.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in analog and mixed-signal IPs such as PCIe, UCIe, SerDes, HBM or DDR PHYs in advanced technology nodes.
- Experience negotiating technical specifications and managing technical deliverables with IP vendors.
Desired Qualifications
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience across architectural requirements, physical design, packaging and board constraints and system considerations for high speed IO and memory PHYs.
- Experience planning or utilizing DFT hooks and on-chip telemetry to support silicon health monitoring and bring-up workflows.
- Track record of successfully integrating complex Ios and mixed signal IPs into an SoC and experience in post-Si taking SoCs to production quality.
- Proven expertise managing end-to-end technical evaluations, performance assessment, and QA sign-offs with third-party analog IP vendors.
Benefits
- Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products.
- Contribute to the innovation behind products loved by millions worldwide.
- Shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
- Empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
- Opportunity to work on cutting-edge AI models, unparalleled computing power, and essential platforms for developers.
- Work on development of TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
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