Senior Staff Verification Engineer (DDR/LPDDR)-18604
Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing
In short
Synopsys is looking for an experienced Senior Staff Verification Engineer to define and execute verification test plans for DDR PHY and memory subsystem IP blocks. The role involves designing System Verilog testbenches using UVM, writing assertions, debugging simulation failures, and mentoring junior engineers. This position requires a Bachelor's degree in EE or CE with 8+ years of ASIC verification experience and proficiency in UVM and System Verilog.
Responsibilities
- Define and track verification test plans for DDR PHY and memory subsystem IP blocks, translating architecture specs into executable verification strategies
- Design and write constrained-random System Verilog testbenches using UVM, building reusable verification components that scale across product families
- Write System Verilog assertions and functional coverage models to close coverage gaps and catch protocol violations
- Debug RTL and gate-level simulation failures, working with design engineers to root-cause issues in complex memory interface logic
- Perform code coverage analysis and drive coverage closure, identifying untested paths and corner cases that matter
- Mentor verification engineers earlier in their careers, reviewing test benches, debugging strategies, and verification plans
- Integrate AI-assisted verification tools and workflows into the team's methodology
Requirements
- Bachelor’s degree in electrical engineering or computer engineering with 8+ years of hands-on ASIC verification experience
- Deep proficiency in UVM methodology and System Verilog, you have built test benches that found bugs
- Strong understanding of DDR memory architecture and DDR PHY design, including timing, training, and calibration flows
- Working knowledge of DFI protocol, memory controllers, or memory subsystem integration
- Solid scripting ability in Perl or Python for automation, result parsing, and flow development
- Proven debugging skills across RTL and gate-level simulations
Desired Qualifications
- Experience with AI-assisted verification tools and workflows is a plus
Benefits
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.
- This role may be eligible for an annual bonus, equity, and other discretionary bonuses.
- Comprehensive health, wellness, and financial benefits as part of a competitive total rewards package.
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Company
Synopsys Inc
Job Posted
2 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Sunnyvale, United States
Qualification
Bachelor
Applicants
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