The Job

Security RTL Design Engineer-Sr Lead/Staff

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

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In short

Qualcomm seeks a senior/staff Security RTL Design Engineer in Bangalore to lead the design of secure hardware IPs for next-generation SoCs, focusing on cryptographic accelerators, Root of Trust, and secure enclaves. The role involves the full front-end RTL development cycle, requiring expertise in SystemVerilog, security threats, and ASIC design fundamentals.

Responsibilities

  • Lead micro-architecture definition and RTL design ownership for hardware security modules, cryptographic engines, and security subsystems.
  • Translate architecture requirements, software use cases, threat-model inputs, and interface specifications into clean micro-architecture specifications.
  • Implement high-quality SystemVerilog RTL for blocks such as AES, SHA, ECC/RSA accelerators, TRNG, key management, secure boot logic, access-control logic, and anti-tamper features.
  • Incorporate secure design techniques, including side-channel mitigation, fault-injection resistance, secure state-machine design, zeroization, privilege checks, and debug lockdown mechanisms.
  • Collaborate with architecture, verification, physical design, DFT, firmware, software, and SoC integration teams to meet security, performance, area, power, and schedule goals.
  • Qualify RTL through front-end design checks such as lint, clock-domain crossing, reset-domain crossing, synthesis, DFT, low-power, formal, and equivalence-readiness reviews.
  • Support performance, latency, bandwidth, buffer sizing, and configuration tuning for security IPs and related system interfaces.
  • Participate in full-chip integration, emulation, silicon bring-up, post-silicon debug, and validation of hardware security features.
  • Contribute to threat-model reviews, security design reviews, standards alignment, and certification-readiness activities.
  • Mentor junior engineers and improve RTL design methodology, design review quality, reusable collateral, and secure-by-construction design practices.

Requirements

  • Strong VLSI logic design expertise with deep ownership of complex SoC or IP-level RTL design.
  • Hands-on experience in SystemVerilog/Verilog RTL coding, micro-architecture, front-end ASIC design flow, and design convergence.
  • Practical hardware security design experience in cryptographic hardware, Root of Trust, secure enclaves, secure processors, key management, or equivalent security IP.
  • Strong understanding of cryptographic acceleration and secure datapath/control design, including AES, SHA, RSA/ECC, TRNG, secure boot, and lifecycle-controlled access paths.
  • Good understanding of side-channel and fault attack countermeasures, secure state machines, privilege separation, tamper resistance, and physical security techniques.
  • Working knowledge of on-chip interconnect and register-access protocols such as APB, AHB, AXI, ACE, or ACE-Lite.
  • Good understanding of clock/reset domains, clock gating, low-power intent, debug infrastructure, and SoC integration constraints.
  • Experience with ASIC convergence activities such as synthesis, static timing analysis, lint, CDC/RDC, DFT, low-power checks, formal verification, and LEC.
  • Strong debugging, analytical thinking, problem solving, communication, and cross-site collaboration skills.
  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
  • OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  • OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Desired Qualifications

  • Experience with security certifications or standards such as FIPS, Common Criteria, or equivalent product security review processes.
  • Experience with automotive, mobile, edge AI, server, or high-assurance security solutions.
  • Knowledge of RISC-V or Arm secure processors, Trusted Execution Environments, secure monitor flows, or secure enclave architectures.
  • Experience with advanced process nodes such as 7 nm and below, including physical design interaction and timing/power closure trade-offs.
  • Experience in designs optimized for low power, including dynamic clock gating, memory retention, memory power collapse, and logic power collapse.
  • Proficiency in Python, Tcl, Perl, C, C++, or SystemC for automation, debug utilities, performance models, or design collateral generation.
  • Working knowledge of functional coverage, assertions, formal property checks, and security-oriented verification planning.

Benefits

  • Qualcomm is an equal opportunity employer.
  • Qualcomm is committed to providing an accessible process for individuals with disabilities.
  • Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.
  • Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
#RTL Design#Hardware Security#ASIC#SoC#IP Design#Cryptographic Accelerators#Root of Trust#Secure Enclaves#Key Management#Secure Boot#Access Control
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Company

Qualcomm

Job Posted

1 month ago

Employment Type

Full Time

WorkMode

On Site

Experience Level

Senior

Locations

Bangalore, India

Qualification

Bachelor, Master, Doctoral

Applicants

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