Principal R&D Engineer - Enterprise SerDes Physical Implementation
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys seeks a Principal R&D Engineer for Enterprise SerDes Physical Implementation in Agrate Brianza, Italy. This role involves driving the physical implementation of high-speed SerDes IPs from RTL to GDSII, leading a team, and automating implementation flows. The ideal candidate will have 10+ years of experience in digital or physical design with expertise in advanced process nodes and scripting.
Responsibilities
- Drive physical implementation of high-speed SerDes IPs and test chips from RTL to GDSII, including timing closure and physical signoff.
- Lead a small team of engineers through implementation flows, setting technical direction and clearing tapeout blockers.
- Develop timing constraints and design architectures that meet power, area, and performance targets on TSMC 16nm and below.
- Collaborate with front-end, analog, and CAD teams to resolve analog/digital interface challenges.
- Automate implementation flows using Perl, Tcl, and Python across multiple process technologies.
- Own chip-level integration and signoff for mixed-signal IPs before tapeout.
Requirements
- MSEE with 10+ years or BSEE with 12+ years in digital or physical design.
- Experience leading physical implementation through multiple project tapeouts.
- Deep knowledge of the full design cycle from RTL to GDSII, including chip-level integration.
- Proven experience with TSMC 16nm or below, including low-power design techniques.
- Strong scripting skills in Perl, Tcl, or Python with CAD automation experience.
- Solid understanding of digital/mixed-signal verification flows and SOC integration.
- Willingness to travel internationally as required.
Desired Qualifications
- Ability to identify and fix timing report bottlenecks without compromising area or power.
- Proactively communicate and justify potential physical problems with RTL to front-end teams.
- Make informed decisions even without perfect information, prioritizing timely execution.
- Lead by setting clear direction and intervening only when the team encounters unresolvable blockers.
- Value and implement automation to improve efficiency and consistency, especially under tight schedules.
- Experience shipping 56G, 112G, and 224G PAM4/6 SerDes platforms into real products.
Benefits
- Comprehensive medical and healthcare plans.
- ETO and FTO Programs for time away.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- ESPP with a 15% discount on Synopsys common stock.
- Retirement plans (vary by region and country).
- Competitive salaries.
#EDA#chip design#verification#manufacturing#AI#ML#GenAI#Cloud#semiconductors#SerDes#RTL#GDSII#timing closure#physical signoff#TSMC#Python#Tcl#Perl#mixed-signal IP#data center#networking
Company
Synopsys Inc
Job Posted
1 month ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Agrate Brianza, Italy
Qualification
Bachelor, Master
Applicants
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